| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2008-09-13 | Fix mulscc with high bits set in either src1 or src2 | blueswir1 | 1 | -2/+3 |
| 2008-09-11 | Write zeros to high bits of y, based on patch by Vince Weaver | blueswir1 | 1 | -2/+4 |
| 2008-09-10 | Convert rest of ops using float32 to TCG, remove FT0 and FT1 | blueswir1 | 1 | -35/+16 |
| 2008-09-10 | Partially convert float128 conversion ops to TCG | blueswir1 | 1 | -8/+6 |
| 2008-09-10 | Convert basic 64 bit VIS ops to TCG | blueswir1 | 1 | -46/+65 |
| 2008-09-10 | Convert basic 32 bit VIS ops to TCG | blueswir1 | 1 | -76/+38 |
| 2008-09-10 | Convert basic float32 ops to TCG | blueswir1 | 1 | -150/+247 |
| 2008-09-09 | Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG | blueswir1 | 1 | -8/+23 |
| 2008-09-06 | Fix a typo in fpsub32 | blueswir1 | 1 | -1/+1 |
| 2008-09-06 | Convert most env fields to TCG registers | blueswir1 | 1 | -95/+91 |
| 2008-09-06 | Silence gcc warning about constant overflow | blueswir1 | 1 | -2/+2 |
| 2008-09-02 | Fix sign extension problems with smul and umul (Vince Weaver) | blueswir1 | 1 | -4/+4 |
| 2008-09-01 | Fix y register loads and stores | blueswir1 | 1 | -18/+16 |
| 2008-08-29 | Fix FCC handling for Sparc64 target, initial patch by Vince Weaver | blueswir1 | 1 | -4/+2 |
| 2008-08-21 | Fix wrwim masking (Luis Pureza) | blueswir1 | 1 | -0/+3 |
| 2008-08-21 | Use initial CPU definition structure for some CPU fields instead of copying | blueswir1 | 1 | -10/+7 |
| 2008-08-17 | Correct 32bit carry flag for add instruction (Igor Kovalenko) | blueswir1 | 1 | -5/+8 |
| 2008-08-06 | Fix Sparc64 shifts | blueswir1 | 1 | -5/+3 |
| 2008-08-06 | Fix offset handling for ASI loads and stores (Vince Weaver) | blueswir1 | 1 | -3/+1 |
| 2008-07-29 | Fix cmp/subcc/addcc op bugs reported by Vince Weaver | blueswir1 | 1 | -4/+4 |
| 2008-07-20 | Make UA200x features selectable, add MMU types | blueswir1 | 1 | -0/+6 |
| 2008-07-19 | Implement nucleus quad ldda | blueswir1 | 1 | -16/+12 |
| 2008-07-18 | Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. | ths | 1 | -7/+6 |
| 2008-07-18 | wrhpr hstick_cmpr is a store, not a load | blueswir1 | 1 | -3/+2 |
| 2008-07-17 | Support for address masking | blueswir1 | 1 | -22/+36 |
| 2008-07-16 | Flushw can generate exceptions, so save PC & NPC | blueswir1 | 1 | -0/+1 |
| 2008-07-15 | Really fix cas | blueswir1 | 1 | -6/+5 |
| 2008-06-29 | Add instruction counter. | pbrook | 1 | -1/+19 |
| 2008-06-22 | Eliminate cpu_T[0] | blueswir1 | 1 | -9/+9 |
| 2008-06-22 | Eliminate cpu_T[1] | blueswir1 | 1 | -4/+3 |
| 2008-06-21 | Convert some cpu_dst uses (with loads/stores) to cpu_tmp0 | blueswir1 | 1 | -67/+67 |
| 2008-06-21 | Avoid brcond problems, use temps for cpu_src1 & cpu_src2 | blueswir1 | 1 | -35/+32 |
| 2008-06-15 | Avoid temporary variable use across basic blocks for udivx | blueswir1 | 1 | -2/+4 |
| 2008-06-07 | Allow NWINDOWS selection (CPU feature with model specific defaults) | blueswir1 | 1 | -2/+0 |
| 2008-05-29 | MicroSparc I didn't have fsmuld op | blueswir1 | 1 | -0/+1 |
| 2008-05-27 | Free temps | blueswir1 | 1 | -109/+313 |
| 2008-05-26 | More TCG type fixes | blueswir1 | 1 | -11/+8 |
| 2008-05-26 | Fix cas on i386 | blueswir1 | 1 | -1/+1 |
| 2008-05-25 | remove absolete function | bellard | 1 | -5/+0 |
| 2008-05-25 | Nicer debug output | blueswir1 | 1 | -0/+2 |
| 2008-05-24 | More TCGv type fixes. | pbrook | 1 | -1/+2 |
| 2008-05-24 | Fix ARM conditional branch bug. | pbrook | 1 | -31/+30 |
| 2008-05-24 | Fix helper operand type mismatch. | pbrook | 1 | -1/+2 |
| 2008-05-22 | Register op helpers | blueswir1 | 1 | -0/+5 |
| 2008-05-17 | Generate better code for Sparc32 shifts | blueswir1 | 1 | -6/+21 |
| 2008-05-12 | Wrap long lines | blueswir1 | 1 | -86/+175 |
| 2008-05-11 | Remove someexplicit alignment checks (initial patch by Fabrice Bellard) | blueswir1 | 1 | -44/+32 |
| 2008-05-10 | Add a TODO file | blueswir1 | 1 | -8/+0 |
| 2008-05-10 | suppressed fixed registers | bellard | 1 | -21/+8 |
| 2008-05-10 | Fix compiler warnings | blueswir1 | 1 | -3/+0 |
