aboutsummaryrefslogtreecommitdiff
path: root/target-sparc/helper.c
AgeCommit message (Expand)AuthorFilesLines
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
2009-05-10Use dynamical computation for condition codesBlue Swirl1-0/+1
2009-05-02Clarify: dmmuregs[1] is not a typoBlue Swirl1-0/+1
2009-04-28sparc64 fix context value for ITLB faultIgor Kovalenko1-1/+1
2009-04-27sparc64 fix TLB match codeIgor Kovalenko1-7/+7
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori1-0/+1
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir11-2/+3
2009-02-21Turn MMUs and caches off on resetblueswir11-0/+1
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-2/+0
2009-01-26Log reset events (Jan Kiszka)aliguori1-0/+5
2009-01-14Get rid of user_mode_onlyaurel321-1/+0
2009-01-12Fix TLB access (Jakub Jermar)blueswir11-10/+10
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-12-23Better SuperSPARC emulation (Robert Reif)blueswir11-23/+27
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-2/+2
2008-10-07Add static (spotted by sparse)blueswir11-1/+1
2008-10-03Rearrange tick functionsblueswir11-31/+0
2008-09-26Add a generic Niagara machineblueswir11-2/+1
2008-09-26Move also DEBUG_PCALL (see r5085)blueswir11-1/+0
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir11-1/+1
2008-08-29Fix Sparc64 boot on i386 host:blueswir11-242/+0
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir11-26/+10
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir11-41/+44
2008-07-22Add T1 and T2 CPUs, add a Sun4v machineblueswir11-0/+22
2008-07-21Use MMU globals for some MMU trapsblueswir11-3/+17
2008-07-21Fix reset vectorblueswir11-1/+1
2008-07-20Print default and available CPU features separatelyblueswir11-4/+7
2008-07-20Make UA200x features selectable, add MMU typesblueswir11-17/+22
2008-07-19Update TLB miss addressesblueswir11-0/+2
2008-07-17Fix saving and loading of trap stateblueswir11-8/+8
2008-07-16Fix MMU miss trapsblueswir11-2/+2
2008-06-26Fix bogus format, reading uninitialised memory (original patch by Julian Seward)blueswir11-1/+1
2008-06-24Fix Sparc mmu bug seen with NetBSD, based on patch by Cliff Wrightblueswir11-8/+8
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir11-26/+81
2008-05-31Add more SuperSparcsblueswir11-0/+36
2008-05-29MicroSparc I didn't have fsmuld opblueswir11-7/+15
2008-05-27Move non-op functions from op_helper.c to helper.c and vice versa.blueswir11-6/+215
2008-05-12Wrap long linesblueswir11-26/+46
2008-05-10Fix compiler warningsblueswir11-12/+13
2008-05-09CPU feature selection supportblueswir11-15/+189
2008-04-11Remove osdep.c/qemu-img code duplicationaurel321-0/+1
2008-03-29 Move CPU stuff unrelated to translation to helper.cblueswir11-6/+521
2008-03-02 Convert tick operations to TCGblueswir11-3/+3
2008-02-11 Sparc32 MMU register fixes (Robert Reif)blueswir11-1/+1
2007-12-25 Enforce context table alignmentblueswir11-1/+1
2007-11-29 Increase prom size for boot modeblueswir11-1/+1
2007-11-28Use slavio base as boot prom address, rearrange sun4m init codeblueswir11-1/+1
2007-11-17Break up vl.h.pbrook1-0/+31
2007-11-07 CPU specific boot mode (Robert Reif)blueswir11-1/+1
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-11/+14