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path: root/target-sh4/translate.c
AgeCommit message (Expand)AuthorFilesLines
2016-11-01log: Add locking to large logging blocksRichard Henderson1-0/+2
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova1-0/+1
2016-06-05target-*: dfilter support for in_asmRichard Henderson1-1/+2
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov1-6/+15
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova1-1/+1
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-24/+24
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-01-29sh4: Clean up includesPeter Maydell1-0/+1
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-0/+5
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-39/+4
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-3/+4
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+6
2015-10-07target-sh4: Add flags state to insn_startRichard Henderson1-1/+1
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-12/+8
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-9/+5
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-13target-sh4: improve shad instructionAurelien Jarno1-31/+22
2015-09-13target-sh4: improve shld instructionAurelien Jarno1-26/+22
2015-09-13target-sh4: improve cmp/str instructionAurelien Jarno1-12/+5
2015-09-13target-sh4: use deposit in swap.b instructionAurelien Jarno1-6/+2
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-2/+2
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-06-12target-sh4: remove dead codeAurelien Jarno1-1/+0
2015-06-12target-sh4: factorize fmov implementationAurelien Jarno1-9/+4
2015-06-12target-sh4: split out Q and M from of SR and optimize div1Aurelien Jarno1-28/+60
2015-06-12target-sh4: optimize negc using add2 and sub2Aurelien Jarno1-6/+6
2015-06-12target-sh4: optimize subc using sub2Aurelien Jarno1-11/+7
2015-06-12target-sh4: optimize addc using add2Aurelien Jarno1-7/+4
2015-06-12target-sh4: Split out T from SRAurelien Jarno1-124/+89
2015-06-12target-sh4: use bit number for SR constantsAurelien Jarno1-36/+39
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-11/+11
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-5/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+2
2013-12-21target-sh4: Use new qemu_ld/st opcodesAurelien Jarno1-77/+90
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+5
2013-07-09target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPUAndreas Färber1-4/+5
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-3/+4
2013-03-12target-sh4: Introduce SuperHCPU subclassesAndreas Färber1-84/+0
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-23target-sh4: Use mul*2 for dmul*Richard Henderson1-28/+2
2013-02-16target-sh4: Move TCG initialization to SuperHCPU initfnAndreas Färber1-2/+1
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