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path: root/target-sh4/translate.c
AgeCommit message (Expand)AuthorFilesLines
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-2/+2
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-06-12target-sh4: remove dead codeAurelien Jarno1-1/+0
2015-06-12target-sh4: factorize fmov implementationAurelien Jarno1-9/+4
2015-06-12target-sh4: split out Q and M from of SR and optimize div1Aurelien Jarno1-28/+60
2015-06-12target-sh4: optimize negc using add2 and sub2Aurelien Jarno1-6/+6
2015-06-12target-sh4: optimize subc using sub2Aurelien Jarno1-11/+7
2015-06-12target-sh4: optimize addc using add2Aurelien Jarno1-7/+4
2015-06-12target-sh4: Split out T from SRAurelien Jarno1-124/+89
2015-06-12target-sh4: use bit number for SR constantsAurelien Jarno1-36/+39
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-11/+11
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-5/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+2
2013-12-21target-sh4: Use new qemu_ld/st opcodesAurelien Jarno1-77/+90
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+5
2013-07-09target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPUAndreas Färber1-4/+5
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-3/+4
2013-03-12target-sh4: Introduce SuperHCPU subclassesAndreas Färber1-84/+0
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-23target-sh4: Use mul*2 for dmul*Richard Henderson1-28/+2
2013-02-16target-sh4: Move TCG initialization to SuperHCPU initfnAndreas Färber1-2/+1
2013-02-16target-sh4: Introduce QOM realizefn for SuperHCPUAndreas Färber1-2/+3
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-4/+4
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-09-21target-sh4: remove useless codeAurelien Jarno1-4/+0
2012-09-21target-sh4: cleanup DisasContextAurelien Jarno1-30/+26
2012-09-21target-sh4: rework exceptions handlingAurelien Jarno1-6/+12
2012-09-21target-sh4: remove gen_clr_t() and gen_set_t()Aurelien Jarno1-13/+3
2012-09-21target-sh4: optimize swap.wAurelien Jarno1-11/+1
2012-09-21target-sh4: optimize xtrctAurelien Jarno1-1/+0
2012-09-21target-sh4: implement addv and subv using TCGAurelien Jarno1-2/+34
2012-09-21target-sh4: implement addc and subc using TCGAurelien Jarno1-2/+36
2012-09-15target-sh4: switch to AREG0 free modeBlue Swirl1-51/+63
2012-06-04Kill off cpu_state_reset()Andreas Färber1-5/+0
2012-06-04target-sh4: Let cpu_sh4_init() return SuperHCPUAndreas Färber1-2/+2
2012-04-30target-sh4: Start QOM'ifying CPU initAndreas Färber1-2/+0
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