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2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-931/+0
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2015-06-17target-s390x: wire up I/O instructions in TCG modeAlexander Graf1-11/+11
The code handling the I/O instructions for KVM decodes the instruction itself. In TCG mode also pass the full instruction word to the helpers. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-17target-s390x: wire up DIAG IPL in TCG modeAurelien Jarno1-1/+1
DIAG IPL is already implemented for KVM, but not wired from TCG. For that change the format of the instruction so that we can get R1 and R3 numbers in addition to the function code. The diag function can change plenty of things, including CC, so we should enter with a static CC. Also it doesn't set the value of general register 2 to 0 as in the current code. We also need to exit the CPU loop after a reset, which means a new PSW. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement high-word facilityAurelien Jarno1-0/+47
Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement load-and-trap facilityAurelien Jarno1-0/+10
At the same time move the trap code from op_ct into gen_trap and use it for all new functions. The value needs to be stored back to register before the exception, but also before the brcond (as we don't use temp locals). That's why we can't use wout helper. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement miscellaneous-instruction-extensions facilityAurelien Jarno1-0/+3
RISBGN is the same as RISBG, but without setting the condition code. CLT and CLGT are the same as CLRT and CLGRT, but using memory for the second operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement LPDFR and LNDFR instructionsAurelien Jarno1-0/+2
This complete the floating point support sign handling facility. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement TRANSLATE EXTENDED instructionAurelien Jarno1-0/+2
It is part of the basic zArchitecture instructions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement TRANSLATE AND TEST instructionAurelien Jarno1-0/+2
It is part of the basic zArchitecture instructions. Allow it to be call from EXECUTE. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement LOAD FP INTEGER instructionsAurelien Jarno1-0/+4
This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test in the gcc testsuite. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: move SET DFP ROUNDING MODE to the correct facilityAurelien Jarno1-1/+1
It belongs to the DFP rounding facility. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: move STORE CLOCK FAST to the correct facilityAurelien Jarno1-1/+1
STORE CLOCK FAST should be in the SCF facility. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: change CHRL and CGHRL format to RIL-bAurelien Jarno1-2/+2
Change to match the PoP. In practice both format RIL-a and RIL-b have the same fields. They differ on the way we decode the fields, and it's done correctly in QEMU. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: fix CLGIT instructionAurelien Jarno1-1/+1
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the numbers as unsigned, as its name implies. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: implement LAY and LAEY instructionsAurelien Jarno1-0/+3
This complete the general-instructions-extension facility, enable it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: remove facility bit] Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05target-s390x: move a few instructions to the correct facilityAurelien Jarno1-4/+4
LY is part of the long-displacement facility. RISBHG and RISBLG are part of the high-word facility. STCMH is part of the z/Architecture. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-05-13s390x: Add interlocked access facility 1 instructionsAlexander Graf1-0/+16
We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-13s390x: Add some documentation in opcode listAlexander Graf1-0/+21
I find it really hard to grasp what each field in the opcode list means. Slowly walking through its semantics myself, I figured I'd write a small summary at the top of the file to make life easier for me and whoever looks at the file next. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-02-03target-s390: Implement ECAGRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03target-s390: Implement LURA, LURAG, STURGRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03target-s390: Implement EPSWRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03target-s390: Implement SAM specification exceptionRichard Henderson1-4/+4
Also, these are user-mode instructions; allow their use in CONFIG_USER_ONLY. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-11-05s390x: Implement SAM{24,31,64}Alexander Graf1-3/+3
The SAM instructions simply change 2 bits in PSW.MASK to advertise the current memory mode. While we can't fully guarantee that 31 bit mode (or even remotely 24 bit mode) actually work correctly, we don't check whether lpswe modifies these bits, so we shouldn't keep the guest from executing SAM instructions either. This patch implements all SAM instrutions with their actual PSW changing semantics, making more recent Linux kernels boot properly which do issue a SAM31 call during early boot. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Perform COMPARE AND SWAP inlineRichard Henderson1-6/+6
Still no proper solution for CONFIG_USER_ONLY, but the system version is significantly better. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Optimize XCRichard Henderson1-1/+1
Notice XC with same address and convert that to store of zero. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement LOAD/SET FP AND SIGNALRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement SET ROUNDING MODERichard Henderson1-0/+5
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement LCDFRRichard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement CPSDRRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement POPCNTRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement CONVERT FROM LOGICALRichard Henderson1-0/+7
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement CONVERT TO LOGICALRichard Henderson1-0/+7
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement STORE ON CONDITIONRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement LOAD ON CONDITIONRichard Henderson1-0/+5
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement COMPARE AND TRAPRichard Henderson1-0/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement COMPARE RELATIVE LONGRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement PREFETCHRichard Henderson1-0/+5
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement R[NOX]SBGRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement LDGR, LGDRRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement RISBGRichard Henderson1-0/+5
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement COMPARE AND BRANCHRichard Henderson1-0/+19
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Implement BRANCH ON INDEXRichard Henderson1-0/+10
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert SERVCRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert LPSWERichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert STFLRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert STSIRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert SACFRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert STCKERichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert CSPRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05target-s390: Convert STURARichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net>
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