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2013-07-01PPC: Ignore writes to L2CRAlexander Graf1-11/+11
The L2CR register contains a number of bits that either impose configuration which we can't deal with or mean "something is in progress until the bit is 0 again". Since we don't model the former and we do want to accomodate guests using the latter semantics, let's just ignore writes to L2CR. That way guests always read back 0 and are usually happy with that. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Introduce an alias cache for faster lookupsAlexander Graf3-7/+30
When running QEMU with "-cpu ?" we walk through every alias for every target CPU we know about. This takes several seconds on my very fast host system. Let's introduce a class object cache in the alias table. Using that we don't have to go through the tedious work of finding our target class. Instead, we can just go directly from the alias name to the target class pointer. This patch brings -cpu "?" to reasonable times again. Before: real 0m4.716s After: real 0m0.025s Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Fix GDB read on code area for PPC6xxFabien Chouteau1-1/+9
On PPC 6xx, data and code have separated TLBs. Until now QEMU was only looking at data TLBs, which is not good when GDB wants to read code. This patch adds a second call to get_physical_address() with an ACCESS_CODE type of access when the first call with ACCESS_INT fails. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Add dump_mmu() for 6xxFabien Chouteau1-0/+92
"(qemu) info tlb" is a very useful tool for debugging, so I implemented the missing 6xx version. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> [agraf: fix printfs on hwaddr to PRI] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc: Introduce unrealizefn for PowerPCCPUAndreas Färber2-2/+18
Use it to clean up the opcode table, resolving a former TODO from Jocelyn. Also switch from malloc() to g_malloc(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc kvm: save cr registerAlexey Kardashevskiy1-0/+5
This adds a missing code to save CR (condition register) via kvm_arch_put_registers(). kvm_arch_get_registers() already has it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01ppc: do not register IABR SPR twice for 603eHervé Poussineau1-5/+0
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E(). Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01target-ppc: Drop redundant flags assignments from CPU familiesAndreas Färber1-45/+0
Previous code has #define POWERPC_INSNS2_<family> PPC_NONE in some places for macrofied assignment to insns_flags2 field. PPC_NONE is defined as zero though and QOM classes are zero-initialized, so drop any pcc->insns_flags2 = PPC_NONE; assignments. PPC_NONE itself is still in use in translate.c. Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01kvm/openpic: in-kernel mpic supportScott Wood1-0/+6
Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build, fix ppcemb] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Add non-kvm stub fileAlexander Graf2-0/+13
There are cases where a kvm provided function is called from generic hw code that doesn't know whether kvm is available or not. Provide a stub file which can provide simple replacement functions for those cases. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-2/+0
This allows to move the call into CPUState's realizefn. Therefore move the stub into libqemustub.a. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber3-6/+15
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28kvm: Change cpu_synchronize_state() argument to CPUStateAndreas Färber2-2/+2
Change Monitor::mon_cpu to CPUState as well. Reviewed-by: liguang <lig.fnst@cn.fujitsu.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-12KVM: PPC: Add dummy kvm_arch_init_irq_routing()Scott Wood1-0/+4
The common KVM code insists on calling kvm_arch_init_irq_routing() as soon as it sees kernel header support for it (regardless of whether QEMU supports it). Provide a dummy function to satisfy this. Unlike x86, PPC does not have one default irqchip, so there's no common code that we'd stick here. Even if you ignore the routes themselves, which even on x86 are not set up in this function, the initial XICS kernel implementation will not support IRQ routing, so it's best to leave even the general feature flags up to the specific irqchip code. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-18remove some double-includesMichael Tokarev1-2/+0
Some source files #include the same header more than once for no good reason. Remove second #includes in such cases. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-08PPC: Depend behavior of cmp instructions only on instruction encodingAlexander Graf1-16/+16
When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, it still behaves identical to what it does when SF is on. Remove the implicit difference in the code. Also, on most 32bit CPUs we should always treat the compare as 32bit compare, as the CPU will ignore the L bit. This is not true for e500mc, but that's up for a different patch. Reported-by: Torbjorn Granlund <tg@gmplib.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-08PPC: Fix rldclAlexander Graf1-2/+0
The implementation for rldcl tried to always fetch its parameters from the opcode, even though the opcode was already passed in in decoded and different forms. Use the parameters instead, fixing rldcl. Reported-by: Torbjorn Granlund <tg@gmplib.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06target-ppc: Add read and write of PPR SPRAnton Blanchard1-0/+4
Recent Linux kernels save and restore the PPR across exceptions so we need to handle it. Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06target-ppc: Fix invalid SPR read/write warningsAnton Blanchard1-16/+16
Invalid and privileged SPR warnings currently print the wrong address. While fixing that, also make it clear that we are printing both the decimal and hexadecimal SPR number. Before: Trying to read invalid spr 896 380 at 0000000000000714 After: Trying to read invalid spr 896 (0x380) at 0000000000000710 Signed-off-by: Anton Blanchard <anton@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-05-06PPC: Add MMU type for 2.06 with AMR but no TB pagesAlexander Graf2-0/+7
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB MMU capability from the MMU type mask, but not the AMR bit. This leads to us having a new MMU type that we don't check for in our MMU management functions. Add the new type, so that we don't have to worry about breakage there. We're not going to use the TCG MMU management in that case anyway. The long term fix for this will be to move all these MMU management functions to class callbacks. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-27target-ppc: slightly optimize lfiwaxAurelien Jarno1-4/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-26target-ppc: add support for extended mtfsf/mtfsfi formsAurelien Jarno2-22/+41
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new W field to select the upper part of the FPCSR register. For that the helper is changed to handle 64-bit input values and mask with up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit marked as invalid anymore. Instead this is checked in the helper, which therefore needs to access to the insns/insns_flags2. They are added in the DisasContext struct. Finally change all accesses to the opcode fields through extract helpers, prefixed with FP for consistency. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate store doubleword pair instructionsAurelien Jarno1-0/+48
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate load doubleword pair instructionsAurelien Jarno1-0/+48
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate lfiwax instructionAurelien Jarno1-0/+21
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: fix tcg debug error] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate fcpsgn instructionAurelien Jarno1-0/+14
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate prtyw and prtyd instructionsAurelien Jarno1-0/+34
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: fix 32-bit host compile, simplify code] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate cmpb instructionAurelien Jarno3-0/+24
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: add instruction flags for Book I 2.05Aurelien Jarno2-2/+4
.. and enable it on POWER7 CPU. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: optimize fabs, fnabs, fnegAurelien Jarno3-40/+34
fabs, fnabs and fneg are just flipping the bit sign of an FP register, this can be implemented in TCG instead of using softfloat. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Fix dcbz for linux-user on 970Alexander Graf1-1/+1
The default with linux-user for dcbz on 970 is to emulate 32 byte clears. However, redoing the dcbzl support we added a check to not honor the bit in HID5 that sets this. Remove the #ifdef check on linux user, so that we get 32 byte clears again. Reported-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26powerpc: correctly handle fpu exceptions.Tristan Gingold1-11/+12
Raise the exception on the first occurence, do not wait for the next floating point operation. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Synchronize VPA state with KVMDavid Gibson1-0/+120
For PAPR guests, KVM tracks the various areas registered with the H_REGISTER_VPA hypercall. For full emulation, of course, these are tracked within qemu. At present these values are not synchronized. This is a problem for reset (qemu's reset of the VPA address is not pushed to KVM) and will also be a problem for savevm / migration. The kernel now supports accessing the VPA state via the ONE_REG interface, this patch adds code to qemu to use that interface to keep the qemu and KVM ideas of the VPA state synchronized. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Add more stubs for POWER7 PMU registersDavid Gibson2-0/+13
In addition to the performance monitor registers found on nearly all 6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an extra control register (MMCRA). This patch adds stub support for them to qemu - the registers won't do anything, but with this change won't cause illegal instruction traps accessing them. They're also registered with their ONE_REG ids, so their value will be kept in sync with KVM where appropriate. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26pseries: Fixes and enhancements to L1 cache propertiesDavid Gibson3-0/+14
PAPR requires that the device tree's CPU nodes have several properties with information about the L1 cache. We already create two of these properties, but with incorrect names - "[id]cache-block-size" instead of "[id]-cache-block-size" (note the extra hyphen). We were also missing some of the required cache properties. This patch adds the [id]-cache-line-size properties (which have the same values as the block size properties in all current cases). We also add the [id]-cache-size properties. Adding the cache sizes requires some extra infrastructure in the general target-ppc code to (optionally) set the cache sizes for various CPUs. The CPU family descriptions in translate_init.c can set these sizes - this patch adds correct information for POWER7, I'm leaving other CPU types to people who have a physical example to verify against. In addition, for -cpu host we take the values advertised by the host (if available) and use those to override the information based on PVR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26pseries: Fix incorrect calculation of RMA size in certain configurationsDavid Gibson1-1/+25
For the pseries machine, we need to advertise to the guest the size of its RMA - that is the amount of memory it can access with the MMU off. For HV KVM, this is constrained by the hardware limitations on the virtual RMA of one hash PTE per PTE group in the hash page table. We already had code to calculate this, but it was assuming the VRMA page size was the same as the (host) backing page size for guest RAM. In the case of a host kernel configured for 64k base page size, but running on hardware (or firmware) which only allows 4k pages, the hose will do all its allocations with a 64k page size, but still use 4k hardware pages for actual mappings. Usually that's transparent to things running under the host, but in the case of the maximum VRMA size it's not. This patch refines the RMA size calculation to instead use the largest available hardware page size (as reported by the SMMU_INFO call) which is less than or equal to the backing page size. This now gives the correct RMA size in all cases I've tested. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26Enable kvm emulated watchdogBharat Bhushan2-0/+98
Enable the KVM emulated watchdog if KVM supports (use the capability enablement in watchdog handler). Also watchdog exit (KVM_EXIT_WATCHDOG) handling is added. Watchdog state machine is cleared whenever VM state changes to running. This is to handle the cases like return from debug halt etc. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: rebase to current code base, fix non-kvm cases] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Fix narrow-mode add/sub carry outputRichard Henderson1-13/+22
Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need to produce the full 64-bit addition. Simplify the conditions at the top of the functions for when we need a new temporary. Only plain addition is important enough to warrent avoiding the temporary, and the extra tcg move op that would come with it. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Add breakpoint registers for 603 and e300Fabien Chouteau1-0/+34
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450Fabien Chouteau1-11/+11
According to the different user's manuals, the vector offset for system reset (both /HRESET and /SRESET) is 0x00100. This patch may break support of some executables, as the power-on start address may change. For a specific board, if the power-on start address is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this should be fixed in board's initialization code. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: fix nego and subf*o instructionsAurelien Jarno1-1/+1
The overflow computation of nego and subf*o instructions has been broken in commit ffe30937. Contrary to other targets, the instruction is subtract from an not subtract on PowerPC. This patch fixes the issue by using the correct argument in the xor computation. Thanks to Peter Maydell for the hint. With this change the PPC emulation passes the Gwenole Beauchesne testsuite again. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: Remove env->hreset_excp_prefixFabien Chouteau3-33/+12
This value is not needed if we use correctly the MSR[IP] bit. excp_prefix is always 0x00000000, except when the MSR[IP] bit is implemented and set to 1, in that case excp_prefix is 0xfff00000. The handling of MSR[IP] was already implemented but not used at reset because the value of env->msr was changed "manually". The patch uses the function hreg_store_msr() to set env->msr, this ensures a good handling of MSR[IP] at reset, and therefore a good value for excp_prefix. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26PPC: e500: advertise 4.2 MPIC only if KVM supports EPRStuart Yoder2-0/+13
Older KVM versions don't support EPR which breaks guests when we announce MPIC variants that support EPR. Catch that case and expose only MPIC version 2.0 which tells the guest that we don't support the EPR capability yet. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> [agraf: Add comment, route cap check through kvm_ppc.c] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: Enable ISEL on POWER7Aurelien Jarno1-1/+1
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7. Given this is trapped and emulated by the Linux kernel, I guess it went unnoticed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-15memory: move core typedefs to qemu/typedefs.hPaolo Bonzini1-2/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move headers to include/Paolo Bonzini1-3/+3
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-22target-ppc: Use NARROW_MODE macro for tlbieRichard Henderson1-4/+3
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use NARROW_MODE macro for addressesRichard Henderson1-33/+18
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use NARROW_MODE macro for comparisonsRichard Henderson1-25/+16
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use NARROW_MODE macro for branchesRichard Henderson1-38/+24
Removing conditional compilation in the process. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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