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2011-10-30pseries: Allow writes to KVM accelerated TCE tableDavid Gibson1-1/+1
Sufficiently recent kernels include a KVM call to accelerate use of PAPR TCE tables (IOMMU), which are used by PAPR virtual IO devices. This involves qemu mapping the TCE table in from a kernel obtained fd, which currently we do with PROT_READ only. This is a hangover from early (never released) versions of this kernel interface which only permitted read-only mappings and required us to destroy and recreate the table when we needed to clear it from qemu. Now, the kernel permits read-write mappings, and we rely on this to clear the table in spapr_vio_quiesce_one(). However, due to insufficient testing, I forgot to update the actual mapping of the table in kvmppc_create_spapr_tce() to add PROT_WRITE to the mmap(). This patch corrects the oversight. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30KVM: PPC: Override host vmx/vsx/dfp only when information knownAlexander Graf1-3/+9
The -cpu host feature tries to find out the host capabilities based on device tree information. However, we don't always have that available because it's an optional property in dt. So instead of force unsetting values depending on an unreliable source of information, let's just try to be clever about it and not override capabilities when we don't know the device tree pieces. This fixes altivec with -cpu host on YDL PowerStations. Reported-by: Nishanth Aravamudan <nacc@us.ibm.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: Fix up usermode only buildsDavid Gibson1-0/+4
The recent usage of MemoryRegion in kvm_ppc.h breaks builds with CONFIG_USER_ONLY=y. This patch fixes it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30pseries: Correct vmx/dfp handling in both KVM and TCG casesDavid Gibson3-17/+44
Currently, when KVM is enabled, the pseries machine checks if the host CPU supports VMX, VSX and/or DFP instructions and advertises accordingly in the guest device tree. It does this regardless of what CPU is selected on the command line. On the other hand, when in TCG mode, it never advertises any of these facilities, even basic VMX (Altivec) which is supported in TCG. Now that we have a -cpu host option for ppc, it is fairly straightforward to fix both problems. This patch changes the -cpu host code to override the basic cpu spec derived from the PVR with information queried from the host avout VMX, VSX and DFP capability. The pseries code then uses the instruction availability advertised in the cpu state to set the guest device tree correctly for both the KVM and TCG cases. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30PPC: Disable non-440 CPUs for ppcemb targetAlexander Graf1-0/+24
The sole reason we have the ppcemb target is to support MMUs that have less than the usual 4k possible page size. There are very few of these chips and I don't want to add additional QA and testing burden to everyone to ensure that code still works when TARGET_PAGE_SIZE is not 4k. So this patch disables all CPUs except for MMU_BOOKE capable ones from the ppcemb target. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30PPC: Bump qemu-system-ppc to 64-bit physical address spaceAlexander Graf1-1/+1
Some 32-bit PPC CPUs can use up to 36 bit of physical address space. Treat them accordingly in the qemu-system-ppc binary type. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3David Gibson1-0/+4
This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3. This allows -cpu host to be used on these host cpus. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: First cut implementation of -cpu hostDavid Gibson4-1/+33
For convenience with kvm, x86 allows the user to specify -cpu host on the qemu command line, which means make the guest cpu the same as the host cpu. This patch implements the same option for ppc targets. For now, this just read the host PVR (Processor Version Register) and selects one of our existing CPU specs based on it. This means that the option will not work if the host cpu is not supported by TCG, even if that wouldn't matter for use under kvm. In future, we can extend this in future to override parts of the cpu spec based on information obtained from the host (via /proc/cpuinfo, the host device tree, or explicit KVM calls). That will let us handle cases where the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated CPU. With appropriate annotation of the CPU specs we'll also then be able to use host cpus under kvm even when there isn't a matching full TCG model. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: Remove broken partial PVR matchingDavid Gibson1-30/+6
The ppc target contains a ppc_find_by_pvr() function, which looks up a CPU spec based on a PVR (that is, based on the value in the target cpu's Processor Version Register). PVR values contain information on both the cpu model (upper 16 bits, usually) and on the precise revision (low 16 bits, usually). ppc_find_by_pvr, as well as making exact PVR matches, attempts to find "close" PVR matches, when we don't have a CPU spec for the exact revision specified. This sounds like a good idea, execpt that the current logic is completely nonsensical. It seems to assume CPU families are subdivided bit by bit in the PVR in a way they just aren't. Specifically, it requires a match on all bits of the specified pvr up to the last non-zero bit. This has the bizarre effect that when the low bits are simply a sequential revision number (a common though not universal pattern), then odd specified revisions must be matched exactly, whereas even specified revisions will also match the next odd revision, likewise for powers of 4, 8 and so forth. To correctly do inexact matching we'd need to re-organize the table of CPU specs to include a mask showing what PVR range the spec is compatible with (similar to the cputable code in the Linux kernel). For now, just remove the bogosity by only permitting exact PVR matches. That at least makes the matching simple and consistent. If we need inexact matching we can add the necessary per-subfamily masks later. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30pseries: Add device tree properties for VMX/VSX and DFP under kvmDavid Gibson2-0/+22
Sufficiently recent PAPR specifications define properties "ibm,vmx" and "ibm,dfp" on the CPU node which advertise whether the VMX vector extensions (or the later VSX version) and/or the Decimal Floating Point operations from IBM's recent POWER CPUs are available. Currently we do not put these in the guest device tree and the guest kernel will consequently assume they are not available. This is good, because they are not supported under TCG. VMX is similar enough to Altivec that it might be trivial to support, but VSX and DFP would both require significant work to support in TCG. However, when running under kvm on a host which supports these instructions, there's no reason not to let the guest use them. This patch, therefore, checks for the relevant support on the host CPU and, if present, advertises them to the guest as well. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: Generalize the kvmppc_get_clockfreq() functionDavid Gibson1-11/+24
Currently the kvmppc_get_clockfreq() function reads the host's clock frequency from /proc/device-tree, which is useful to past to the guest in KVM setups. However, there are some other host properties advertised in the device tree which can also be relevant to the guests. This patch, therefore, replaces kvmppc_get_clockfreq() which can retrieve any named, single integer property from the host device tree's CPU node. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30Set an invalid-bits mask for each SPE instructionsFabien Chouteau1-229/+271
SPE instructions are defined by pairs. Currently, the invalid-bits mask is set for the first instruction, but the second one can have a different mask. example: GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30pseries: Use Book3S-HV TCE acceleration capabilitiesDavid Gibson2-0/+68
The pseries machine of qemu implements the TCE mechanism used as a virtual IOMMU for the PAPR defined virtual IO devices. Because the PAPR spec only defines a small DMA address space, the guest VIO drivers need to update TCE mappings very frequently - the virtual network device is particularly bad. This means many slow exits to qemu to emulate the H_PUT_TCE hypercall. Sufficiently recent kernels allow this to be mitigated by implementing H_PUT_TCE in the host kernel. To make use of this, however, qemu needs to initialize the necessary TCE tables, and map them into itself so that the VIO device implementations can retrieve the mappings when they access guest memory (which is treated as a virtual DMA operation). This patch adds the necessary calls to use the KVM TCE acceleration. If the kernel does not support acceleration, or there is some other error creating the accelerated TCE table, then it will still fall back to full userspace TCE implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30pseries: Allow KVM Book3S-HV on PPC970 CPUSDavid Gibson2-0/+52
At present, using the hypervisor aware Book3S-HV KVM will only work with qemu on POWER7 CPUs. PPC970 CPUs also have hypervisor capability, but they lack the VRMA feature which makes assigning guest memory easier. In order to allow KVM Book3S-HV on PPC970, we need to specially allocate the first chunk of guest memory (the "Real Mode Area" or RMA), so that it is physically contiguous. Sufficiently recent host kernels allow such contiguous RMAs to be allocated, with a kvm capability advertising whether the feature is available and/or necessary on this hardware. This patch enables qemu to use this support, thus allowing kvm acceleration of pseries qemu machines on PPC970 hardware. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de> --- agraf: fix to use memory api
2011-10-30pseries: Support SMT systems for KVM Book3S-HVDavid Gibson3-0/+25
Alex Graf has already made qemu support KVM for the pseries machine when using the Book3S-PR KVM variant (which runs the guest in usermode, emulating supervisor operations). This code allows gets us very close to also working with KVM Book3S-HV (using the hypervisor capabilities of recent POWER CPUs). This patch moves us another step towards Book3S-HV support by correctly handling SMT (multithreaded) POWER CPUs. There are two parts to this: * Querying KVM to check SMT capability, and if present, adjusting the cpu numbers that qemu assigns to cause KVM to assign guest threads to cores in the right way (this isn't automatic, because the POWER HV support has a limitation that different threads on a single core cannot be in different guests at the same time). * Correctly informing the guest OS of the SMT thread to core mappings via the device tree. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: booke timersFabien Chouteau2-0/+66
While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06KVM: PPC: Use HIOR setting for -M pseries with PR KVMAlexander Graf1-3/+22
When running with PR KVM, we need to set HIOR directly. Thankfully there is now a new interface to set registers individually so we can just use that and poke HIOR into the guest vcpu's HIOR register. While at it, this also sets SDR1 because -M pseries requires it to run. With this patch, -M pseries works properly with PR KVM. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Gdbstub: handle read of fpscrFabien Chouteau1-2/+1
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson3-1/+58
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pagesScott Wood2-4/+5
This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: booke206: add "info tlb" supportScott Wood2-0/+90
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06kvm: ppc: booke206: use MMU APIScott Wood2-0/+87
Share the TLB array with KVM. This allows us to set the initial TLB both on initial boot and reset, is useful for debugging, and could eventually be used to support migration. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Enable to use PAPR with PR style KVMAlexander Graf2-0/+45
When running PR style KVM, we need to tell the kernel that we want to run in PAPR mode now. This means that we need to pass some more register information down and enable papr mode. We also need to align the HTAB to htab_size boundary. Using this patch, -M pseries works with kvm even on non-hv kvm implementations, as long as the preceding kernel patches are in. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - match on CONFIG_PSERIES v2 -> v3: - remove HIOR pieces from PAPR patch (ABI breakage)
2011-10-06PPC: KVM: Add stubs for kvm helper functionsAlexander Graf1-0/+26
We have a bunch of helper functions that don't have any stubs for them in case we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can optimize them out pretty well, but we should really provide them. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use uint64_t for clockfreq
2011-10-06PPC: KVM: Remove kvmppc_read_host_propertyAlexander Graf2-46/+0
We just got rid of the last user of kvmppc_read_host_property, so we can now safely remove it. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: KVM: Add generic function to read host clockfreqAlexander Graf2-0/+68
We need to find out the host's clock-frequency when running on KVM, so let's export a respective function. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - enable 64bit values
2011-10-06PPC: bamboo: Move host fdt copy to targetAlexander Graf2-31/+0
We have some code in generic kvm_ppc.c that is only used by 440. Move to the 440 specific device code. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-4/+3
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-23core: remove qemu_service_ioFrediano Ziglio1-1/+1
qemu_service_io was mainly an alias to qemu_notify_event, currently used only by PPC for timer hack, so call qemu_notify_event directly. Signed-off-by: Frediano Ziglio <freddy77@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-16Remove blanks before \n in output stringsStefan Weil1-1/+1
Those blanks violate the coding conventions, see scripts/checkpatch.pl. Blanks missing after colons in the changed lines were added. This patch does not try to fix tabs, long lines and other problems in the changed lines, therefore checkpatch.pl reports many violations. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-23PPC: E500: Set ESR valuesAlexander Graf1-0/+6
When an exception occurs on BookE, we need to set ESR bits to expose to the guest information on what exactly happened. Add the obvious ones. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-23PPC: E500: Inject SPE exception on invalid SPE accessAlexander Graf1-39/+39
When accessing an SPE instruction despite it being not available, throw an SPE exception instead of an APU exception. That way the guest knows what's going on and actually uses SPE. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-23PPC: E500: Add ESR bit definitionsAlexander Graf2-3/+18
The BookE spec specifies a number of ESR bits. Add defines for them so we can use them later on. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori3-6/+6
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl3-4/+4
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-05Avoid allocating TCG resources in non-TCG modeJan Kiszka1-1/+3
Do not allocate TCG-only resources like the translation buffer when running over KVM or XEN. Saves a "few" bytes in the qemu address space and is also conceptually cleaner. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-30exec.h cleanupBlue Swirl2-35/+6
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-12target-alpha, target-ppc: Remove unnecessary setjmp.h includePeter Maydell1-2/+0
Remove the include of setjmp.h from the cpu.h of target-alpha and target-ppc. This is unnecessary because cpu-defs.h already includes this header; this change brings these two targets into line with all the rest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl6-176/+284
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
2011-06-26Remove exec-all.h include directivesBlue Swirl3-3/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2-11/+12
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl1-2/+2
Before the next patch, fix coding style of the areas affected. Change the type of the return value from cpu_has_work() and qemu_cpu_has_work() to bool. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu_loop_exit: avoid using AREG0Blue Swirl1-1/+1
Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-20kvm: ppc: Drop KVM_CAP build dependenciesJan Kiszka1-14/+0
No longer needed with accompanied kernel headers. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-06-20kvm: ppc: Drop CONFIG_KVM_PPC_PVRJan Kiszka1-9/+0
Required header support is now unconditionally available. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-06-17PPC: move TLBs to their own arraysAlexander Graf5-35/+67
Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17PPC: E500: Use MAS registers instead of internal TLB representationAlexander Graf3-135/+200
The natural format for e500 cores to do TLB manipulation with are the MAS registers. Instead of converting them into some internal representation and back again when the guest reads them, we can just keep the data identical to the way the guest passed it to us. The main advantage of this approach is that we're getting closer to being able to share MMU data with KVM using shared memory, so that we don't need to copy lots of MMU data back and forth all the time. For this to work however, another patch is required that gets rid of the TLB union, as that destroys our memory layout that needs to be identical with the kernel one. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17PPC: Only set lower 32bits with mtmsrAlexander Graf1-11/+6
As Nathan pointed out correctly, the mtmsr instruction does not modify the high 32 bits of MSR. It also doesn't matter if SF is set or not, the instruction always behaves the same. This patch moves it a bit closer to the spec. Reported-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17target-ppc: Handle memory-forced I/O controller accessHervé Poussineau1-0/+16
On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07F is special-cased as memory-forced I/O controller access. It is supposed to be checked immediately if T=1, bypassing all protection mechanisms and acting cache-inhibited and global. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Simplified by avoiding reindentation. Added explanatory comments. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-08Fix compilation warning due to missing header for sigaction (followup)Alexandre Raymond1-1/+0
This patch removes all references to signal.h when qemu-common.h is included as they become redundant. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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