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2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl3-4/+4
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-05Avoid allocating TCG resources in non-TCG modeJan Kiszka1-1/+3
Do not allocate TCG-only resources like the translation buffer when running over KVM or XEN. Saves a "few" bytes in the qemu address space and is also conceptually cleaner. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-30exec.h cleanupBlue Swirl2-35/+6
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-12target-alpha, target-ppc: Remove unnecessary setjmp.h includePeter Maydell1-2/+0
Remove the include of setjmp.h from the cpu.h of target-alpha and target-ppc. This is unnecessary because cpu-defs.h already includes this header; this change brings these two targets into line with all the rest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl6-176/+284
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
2011-06-26Remove exec-all.h include directivesBlue Swirl3-3/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2-11/+12
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl1-2/+2
Before the next patch, fix coding style of the areas affected. Change the type of the return value from cpu_has_work() and qemu_cpu_has_work() to bool. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu_loop_exit: avoid using AREG0Blue Swirl1-1/+1
Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-20kvm: ppc: Drop KVM_CAP build dependenciesJan Kiszka1-14/+0
No longer needed with accompanied kernel headers. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-06-20kvm: ppc: Drop CONFIG_KVM_PPC_PVRJan Kiszka1-9/+0
Required header support is now unconditionally available. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-06-17PPC: move TLBs to their own arraysAlexander Graf5-35/+67
Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17PPC: E500: Use MAS registers instead of internal TLB representationAlexander Graf3-135/+200
The natural format for e500 cores to do TLB manipulation with are the MAS registers. Instead of converting them into some internal representation and back again when the guest reads them, we can just keep the data identical to the way the guest passed it to us. The main advantage of this approach is that we're getting closer to being able to share MMU data with KVM using shared memory, so that we don't need to copy lots of MMU data back and forth all the time. For this to work however, another patch is required that gets rid of the TLB union, as that destroys our memory layout that needs to be identical with the kernel one. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17PPC: Only set lower 32bits with mtmsrAlexander Graf1-11/+6
As Nathan pointed out correctly, the mtmsr instruction does not modify the high 32 bits of MSR. It also doesn't matter if SF is set or not, the instruction always behaves the same. This patch moves it a bit closer to the spec. Reported-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-17target-ppc: Handle memory-forced I/O controller accessHervé Poussineau1-0/+16
On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07F is special-cased as memory-forced I/O controller access. It is supposed to be checked immediately if T=1, bypassing all protection mechanisms and acting cache-inhibited and global. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Simplified by avoiding reindentation. Added explanatory comments. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-08Fix compilation warning due to missing header for sigaction (followup)Alexandre Raymond1-1/+0
This patch removes all references to signal.h when qemu-common.h is included as they become redundant. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-06-03Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno2-12/+10
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: fix mpc8544ds pci default devices Fix segfault on screendump with -nographic PPC: install mpc8544ds.dtb PPC: fix sregs usage on booke ppc: Fix compilation for ppc64-softmmu
2011-06-03target-ppc: remove old CONFIG_SOFTFLOAT #ifdefAurelien Jarno3-15/+0
target-ppc has been switched to softfloat only long ago, but a few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them. Cc: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03PPC: fix sregs usage on bookeAlexander Graf1-6/+4
When compiling qemu with kvm support on BookE PPC machines, I get the following error: cc1: warnings being treated as errors /tmp/qemu/target-ppc/kvm.c: In function 'kvm_arch_get_registers': /tmp/qemu/target-ppc/kvm.c:188: error: unused variable 'sregs' This is due to overly ambitious #ifdef'ery introduced in 90dc88. Fix it by keeping code that doesn't depend on new headers alive for the compiler, but never executed due to failing capability checks. CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-03ppc: Fix compilation for ppc64-softmmuStefan Weil1-6/+6
When QEMU was configured with --enable-debug-tcg, compilation fails in spr_write_booke206_mmucsr0() and in spr_write_booke_pid(). Similar changes are also needed in conditional code which is normally unused. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-23Merge branch 'trivial-patches' of git://repo.or.cz/qemu/stefanhaAurelien Jarno1-1/+1
* 'trivial-patches' of git://repo.or.cz/qemu/stefanha: Fix typos in comments (chek -> check) hw/sd.c: Don't complain about SDIO commands CMD52/CMD53 hw/realview.c: Remove duplicate #include line piix_pci: fix piix3_set_irq_pic()
2011-05-23Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno2-7/+6
* 'ppc-next' of git://repo.or.cz/qemu/agraf: Fix a bug in mtsr/mtsrin emulation on ppc64 pSeries: Clean up write-only variables w32: Fix compilation and replace non-portable usage of ulong
2011-05-22Fix typos in comments (chek -> check)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-22Delete unused tb_invalidate_page_rangeBlue Swirl1-1/+0
tb_invalidate_page_range() was intended to be used to invalidate an area of a TB which the guest explicitly flushes from i-cache. However, QEMU detects writes to code areas where TBs have been generated, so his has never been useful. Delete the function, adjust callers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-20Fix a bug in mtsr/mtsrin emulation on ppc64David Gibson1-5/+4
Early ppc64 CPUs include a hack to partially simulate the ppc32 segment registers, by translating writes to them into writes to the SLB. This is not used by any current Linux kernel, but it is used by the openbios used in the qemu mac99 model. Commit 81762d6dd0d430d87024f2c83e9c4dcc4329fb7d, cleaning up the SLB handling introduced a bug in this code, breaking the openbios currently in qemu. Specifically, there was an off by one error bitshuffling the register format used by mtsr into the format needed for the SLB load, causing the flag bits to end up in the wrong place. This caused the storage keys to be wrong under openbios, meaning that the translation code incorrectly thought a legitimate access was a permission violation. This patch fixes the bug, at the same time it fixes some build bug in the MMU debugging code (only exposed when DEBUG_MMU is enabled). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-20w32: Fix compilation and replace non-portable usage of ulongStefan Weil1-2/+2
ulong is undefined for w32 (and maybe other) compilations. Replace it by uintptr_t (which also fixes compilation for w64 and is a better choice for pointer to integer conversions). Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-14Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno7-159/+1382
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: Qdev'ify e500 pci PPC MPC7544DS: Use new TLB helper function PPC: Implement e500 (FSL) MMU PPC: Add another 64 bits to instruction feature mask PPC: Add GS MSR definition PPC: Make MPC8544DS emulation work w/o KVM PPC: Make MPC8544DS obey -cpu switch Fix off-by-one error in sizing pSeries hcall table ppc64: Fix out-of-tree builds kvm: ppc: warn user on PAGE_SIZE mismatch kvm: ppc: detect old headers monitor: add PPC BookE SPRs kvm: ppc: fixes for KVM_SET_SREGS on init ppc64: Don't try to build sPAPR RTAS on Darwin Place pseries vty devices at addresses more similar to existing machines Make pSeries 'model' property more closely resemble real hardware pseries: Increase maximum CPUs to 256
2011-05-12PPC: Implement e500 (FSL) MMUAlexander Graf6-113/+1020
Most of the code to support e500 style MMUs is already in place, but we're missing on some of the special TLB0-TLB1 handling code and slightly different TLB modification. This patch adds support for the FSL style MMU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12PPC: Add another 64 bits to instruction feature maskAlexander Graf3-39/+110
To enable quick runtime detection of instruction groups to the currently selected CPU emulation, we have a feature mask of what exactly the respective instruction supports. This feature mask is 64 bits long and we just successfully exceeded those 64 bits. To add more features, we need to think of something. The easiest solution that came to my mind was to simply add another 64 bits that we can also match on. Since the comparison is only done on start of the qemu process to generate an internal opcode calling table, we should be fine on any performance penalties here. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12PPC: Add GS MSR definitionAlexander Graf1-0/+2
The BookE specification defines MSR bit 28 as Guest State. Add it to the list of MSR macros. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-09kvm: ppc: detect old headersAlexander Graf1-1/+15
When compiling Qemu with older kernel headers, the PVR setting mechanism isn't available yet. Unfortunately, back then I didn't add a capability we could check against, so all we can do is add a configure test to see if we support PVR setting. For BookE, we don't care yet. This fixes compilation errors with KVM enabled on older kernel headers (like 2.6.32). Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-09monitor: add PPC BookE SPRsScott Wood3-12/+214
Read them via KVM_GET_SREGS in kvm_arch_get_registers(), and display them in "info registers". Also get CR and PID from the existing KVM_GET_REGS. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-09kvm: ppc: fixes for KVM_SET_SREGS on initScott Wood1-3/+30
Classic/server ppc has had SREGS for a while now (though I think not always?), but it's still missing for booke. Check the capability before calling KVM_SET_SREGS. Without this, booke kvm fails to boot as of commit 84b4915dd2c0eaa86c970ffc42a68ea8ba9e48b5 (kvm: Handle kvm_init_vcpu errors). Also, don't write random stack state into the non-PVR sregs fields -- have kvm fill it in first. Eventually booke will have sregs and it will have its own capability to be tested here. However, we will want a way for platform code to request to look like the actual CPU we're running on, especially if SoC devices are being directly assigned. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-08Fix typos in comments (instanciation -> instantiation)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08Fix typo in comment (embeded -> embedded)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-04-20Remove unused function parameter from cpu_restore_stateStefan Weil1-1/+1
The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil1-2/+1
Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-17target-ppc: fix SPE comparison functionsAurelien Jarno1-13/+13
efstst*() functions are fast SPE funtions which do not take into account special values (infinites, NaN, etc.), while efscmp*() functions are IEEE754 compliant. Given that float32_*() functions are IEEE754 compliant, the efscmp*() functions are correctly implemented, while efstst*() are not. This patch reverse the implementation of this two groups of functions and fix the comments. It also use float32_eq() instead of float32_eq_quiet() as qNaNs should not be ignored. Cc: Alexander Graf <agraf@suse.de> Cc: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17softfloat: rename float*_eq() into float*_eq_quiet()Aurelien Jarno1-2/+2
float*_eq functions have a different semantics than other comparison functions. Fix that by first renaming float*_quiet() into float*_eq_quiet(). Note that it is purely mechanical, and the behaviour should be unchanged. That said it clearly highlight problems due to this different semantics, they are fixed later in this patch series. Cc: Alexander Graf <agraf@suse.de> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-ppc: remove #ifdef FLOAT128Aurelien Jarno1-20/+0
Now that PPC defaults to softfloat which always provides float128 support, there is no need to keep two version of the code, depending if float128 support is available or not. Suggested by Peter Maydell. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil1-1/+1
tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-08ppce500_mpc8544ds: Fix compile with --enable-debug and --disable-kvmDavid Gibson1-0/+9
When configured with --enable-debug, we compile without optimization. This means that the function mpc8544_copy_soc_cell() in ppce500_mpc8544ds.c is not optimized out, even though it is never called without kvm. That in turn causes a link failure, because it calls the function kvmppc_read_host_property() which is in kvm_ppc.o and therefore not included in a --disable-kvm build. This patch fixes the problem by providing a dummy stub for kvmppc_read_host_property() in kvm_ppc.h when !CONFIG_KVM. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-08Use existing helper function to implement popcntd instructionDavid Gibson1-13/+1
The recent patches adding partial support for POWER7 cpu emulation included implementing the popcntd instruction. The support for this was open coded, but host-utils.h already included a function implementing an equivalent population count function, which uses a gcc builtin (which can use special host instructions) if available. This patch makes the popcntd implementation use the existing, potentially faster, implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PAPR VPA functions for pSeries shared processor partitionsDavid Gibson1-0/+7
Shared-processor partitions are those where a CPU is time-sliced between partitions, rather than being permanently dedicated to a single partition. qemu emulated partitions, since they are just scheduled with the qemu user process, behave mostly like shared processor partitions. In order to better support shared processor partitions (splpar), PAPR defines the "VPA" (Virtual Processor Area), a shared memory communication channel between the hypervisor and partitions. There are also two additional shared memory communication areas for specialized purposes associated with the VPA. A VPA is not essential for operating an splpar, though it can be necessary for obtaining accurate performance measurements in the presence of runtime partition switching. Most importantly, however, the VPA is a prerequisite for PAPR's H_CEDE, hypercall, which allows a partition OS to give up it's shared processor timeslices to other partitions when idle. This patch implements the VPA and H_CEDE hypercalls in qemu. We don't implement any of the more advanced statistics which can be communicated through the VPA. However, this is enough to make normal pSeries kernels do an effective power-save idle on an emulated pSeries, significantly reducing the host load of a qemu emulated pSeries running an idle guest OS. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PAPR CRQ hypercallsBen Herrenschmidt1-0/+11
This patch implements the infrastructure and hypercalls necessary for the PAPR specified CRQ (Command Request Queue) mechanism. This general request queueing system is used by many of the PAPR virtual IO devices, including the virtual scsi adapter. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Virtual hash page table handling on pSeries machineDavid Gibson2-8/+30
On pSeries logical partitions, excepting the old POWER4-style full system partitions, the guest does not have direct access to the hardware page table. Instead, the pagetable exists in hypervisor memory, and the guest must manipulate it with hypercalls. However, our current pSeries emulation more closely resembles the old style where the guest must set up and handle the pagetables itself. This patch converts it to act like a modern partition. This involves two things: first, the hash translation path is modified to permit the has table to be stored externally to the emulated machine's RAM. The pSeries machine init code configures the CPUs to use this mode. Secondly, we emulate the PAPR hypercalls for manipulating the external hashed page table. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Add POWER7 support for ppcDavid Gibson3-0/+129
This adds emulation support for the recent POWER7 cpu to qemu. It's far from perfect - it's missing a number of POWER7 features so far, including any support for VSX or decimal floating point instructions. However, it's close enough to boot a kernel with the POWER7 PVR. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Support 1T segments on ppcDavid Gibson2-12/+45
Traditionally, the "segments" used for the two-stage translation used on powerpc MMUs were 256MB in size. This was the only option on all hash page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page table based cpus. However, newer 64-bit cpus also permit 1TB segments This patch adds support for 1TB segment translation to the qemu code. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Better factor the ppc hash translation pathDavid Gibson2-48/+20
Currently the path handling hash page table translation in get_segment() has a mix of common and 32 or 64 bit specific code. However the division is not done terribly well which results in a lot of messy code flipping between common and divided paths. This patch improves the organization, consolidating several divided paths into one. This in turn allows simplification of some code in get_segment(), removing a number of ugly interim variables. This new factorization will also make it easier to add support for the 1T segments added in newer CPUs. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Use "hash" more consistently in ppc mmu codeDavid Gibson2-50/+50
Currently, get_segment() has a variable called hash. However it doesn't (quite) get the hash value for the ppc hashed page table. Instead it gets the hash shifted - effectively the offset of the hash bucket within the hash page table. As well, as being different to the normal use of plain "hash" in the architecture documentation, this usage necessitates some awkward 32/64 dependent masks and shifts which clutter up the path in get_segment(). This patch alters the code to use raw hash values through get_segment() including storing raw hashes instead of pte group offsets in the ctx structure. This cleans up the path noticeably. This does necessitate 32/64 dependent shifts when the hash values are taken out of the ctx structure and used, but those paths already have 32/64 bit variants so this is less awkward than it was in get_segment(). Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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