aboutsummaryrefslogtreecommitdiff
path: root/target-ppc
AgeCommit message (Expand)AuthorFilesLines
2016-06-16os-posix: include sys/mman.hPaolo Bonzini1-1/+0
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth1-0/+3
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth2-4/+13
2016-06-14ppc: Provide function to get CPU class of the host CPUThomas Huth2-5/+21
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth3-3/+7
2016-06-07Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-2/+0
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz1-2/+0
2016-06-07ppc: Do not take exceptions on unknown SPRs in privileged modeBenjamin Herrenschmidt1-2/+9
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt3-0/+57
2016-06-07ppc: Fix slbia decodeBenjamin Herrenschmidt1-1/+1
2016-06-07ppc: Fix mtmsr decodingBenjamin Herrenschmidt1-1/+1
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt2-2/+5
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt1-0/+18
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt4-44/+31
2016-06-07ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processorsBenjamin Herrenschmidt1-0/+8
2016-06-07ppc: Properly tag the translation cache based on MMU modeBenjamin Herrenschmidt1-1/+1
2016-06-07target-ppc: fixup bitrot in mmu_helper.c debug statementsMark Cave-Ayland1-14/+24
2016-06-07ppc: fix hrfid, tlbia and slbia privilegeCédric Le Goater1-3/+3
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt2-4/+8
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt3-5/+22
2016-06-07target-ppc/fpu_helper: Fix efscmp* instructions handlingTalha Imran1-1/+1
2016-06-05target-*: dfilter support for in_asmRichard Henderson1-1/+2
2016-05-30ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt1-2/+2
2016-05-30ppc: Get out of emulation on SMT "OR" opsBenjamin Herrenschmidt1-3/+18
2016-05-30ppc: Fix sign extension issue in mtmsr(d) emulationMichael Neuling1-2/+2
2016-05-30ppc: Change 'invalid' bit mask of tlbiel and tlbieBenjamin Herrenschmidt1-2/+4
2016-05-30ppc: tlbie, tlbia and tlbisync are HV onlyBenjamin Herrenschmidt1-3/+3
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt7-12/+71
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt5-25/+63
2016-05-30ppc: Remove MMU_MODEn_SUFFIX definitionsBenjamin Herrenschmidt1-3/+0
2016-05-27spapr_iommu: Finish renaming vfio_accel to need_vfioAlexey Kardashevskiy1-1/+1
2016-05-27PPC/KVM: early validation of vcpu idGreg Kurz1-0/+8
2016-05-27target-ppc: Cleanups to rldinm, rldnm, rldimiRichard Henderson1-45/+46
2016-05-27target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotateRichard Henderson1-102/+70
2016-05-27target-ppc: Use movcond in iselRichard Henderson1-18/+11
2016-05-27target-ppc: Correct KVM synchronization for ppc_hash64_set_external_hpt()David Gibson1-2/+0
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini11-2/+12
2016-05-19qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini4-1/+5
2016-05-19hw: move CPU state serialization to migration/cpu.hPaolo Bonzini1-0/+1
2016-05-19ppc: use PowerPCCPU instead of CPUPPCStatePaolo Bonzini1-54/+38
2016-05-19target-ppc: make cpu-qom.h not target specificPaolo Bonzini2-163/+161
2016-05-19target-ppc: do not make PowerPCCPUClass depend on target-specific symbolsPaolo Bonzini1-4/+0
2016-05-19target-ppc: do not use target_ulong in cpu-qom.hPaolo Bonzini5-6/+5
2016-05-19cpu: make cpu-qom.h only include-able from cpu.hPaolo Bonzini1-1/+0
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov1-5/+15
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota1-1/+1
2016-04-18ppc: Fix migration of the XER registerThomas Huth1-1/+1
2016-04-18ppc: Fix the bad exception NIP value and the range check in LSWXThomas Huth1-2/+3
2016-04-18ppc: Fix the range check in the LSWI instructionThomas Huth2-4/+12
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater3-3/+58
generated by cgit v1.1 at 2024-12-24 17:24:04 +0000