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2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic1-59/+61
This patch modifies SoftFloat library so that it can be configured in run-time in relation to the meaning of signaling NaN bit, while, at the same time, strictly preserving its behavior on all existing platforms. Background: In floating-point calculations, there is a need for denoting undefined or unrepresentable values. This is achieved by defining certain floating-point numerical values to be NaNs (which stands for "not a number"). For additional reasons, virtually all modern floating-point unit implementations use two kinds of NaNs: quiet and signaling. The binary representations of these two kinds of NaNs, as a rule, differ only in one bit (that bit is, traditionally, the first bit of mantissa). Up to 2008, standards for floating-point did not specify all details about binary representation of NaNs. More specifically, the meaning of the bit that is used for distinguishing between signaling and quiet NaNs was not strictly prescribed. (IEEE 754-2008 was the first floating-point standard that defined that meaning clearly, see [1], p. 35) As a result, different platforms took different approaches, and that presented considerable challenge for multi-platform emulators like QEMU. Mips platform represents the most complex case among QEMU-supported platforms regarding signaling NaN bit. Up to the Release 6 of Mips architecture, "1" in signaling NaN bit denoted signaling NaN, which is opposite to IEEE 754-2008 standard. From Release 6 on, Mips architecture adopted IEEE standard prescription, and "0" denotes signaling NaN. On top of that, Mips architecture for SIMD (also known as MSA, or vector instructions) also specifies signaling bit in accordance to IEEE standard. MSA unit can be implemented with both pre-Release 6 and Release 6 main processor units. QEMU uses SoftFloat library to implement various floating-point-related instructions on all platforms. The current QEMU implementation allows for defining meaning of signaling NaN bit during build time, and is implemented via preprocessor macro called SNAN_BIT_IS_ONE. On the other hand, the change in this patch enables SoftFloat library to be configured in run-time. This configuration is meant to occur during CPU initialization, at the moment when it is definitely known what desired behavior for particular CPU (or any additional FPUs) is. The change is implemented so that it is consistent with existing implementation of similar cases. This means that structure float_status is used for passing the information about desired signaling NaN bit on each invocation of SoftFloat functions. The additional field in float_status is called snan_bit_is_one, which supersedes macro SNAN_BIT_IS_ONE. IMPORTANT: This change is not meant to create any change in emulator behavior or functionality on any platform. It just provides the means for SoftFloat library to be used in a more flexible way - in other words, it will just prepare SoftFloat library for usage related to Mips platform and its specifics regarding signaling bit meaning, which is done in some of subsequent patches from this series. Further break down of changes: 1) Added field snan_bit_is_one to the structure float_status, and correspondent setter function set_snan_bit_is_one(). 2) Constants <float16|float32|float64|floatx80|float128>_default_nan (used both internally and externally) converted to functions <float16|float32|float64|floatx80|float128>_default_nan(float_status*). This is necessary since they are dependent on signaling bit meaning. At the same time, for the sake of code cleanup and simplicity, constants <floatx80|float128>_default_nan_<low|high> (used only internally within SoftFloat library) are removed, as not needed. 3) Added a float_status* argument to SoftFloat library functions XXX_is_quiet_nan(XXX a_), XXX_is_signaling_nan(XXX a_), XXX_maybe_silence_nan(XXX a_). This argument must be present in order to enable correct invocation of new version of functions XXX_default_nan(). (XXX is <float16|float32|float64|floatx80|float128> here) 4) Updated code for all platforms to reflect changes in SoftFloat library. This change is twofolds: it includes modifications of SoftFloat library functions invocations, and an addition of invocation of function set_snan_bit_is_one() during CPU initialization, with arguments that are appropriate for each particular platform. It was established that all platforms zero their main CPU data structures, so snan_bit_is_one(0) in appropriate places is not added, as it is not needed. [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer Society, August 29, 2008. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [leon.alrae@imgtec.com: * cherry-picked 2 chunks from patch #2 to fix compilation warnings] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-06-23ppc: Disable huge page support if it is not available for main RAMThomas Huth1-1/+16
On powerpc, we must only signal huge page support to the guest if all memory areas are capable of supporting huge pages. The commit 2d103aae8765 ("fix hugepage support when using memory-backend-file") already fixed the case when the user specified the mem-path property for NUMA memory nodes instead of using the global "-mem-path" option. However, there is one more case where it currently can go wrong. When specifying additional memory DIMMs without using NUMA, e.g. qemu-system-ppc64 -enable-kvm ... -m 1G,slots=2,maxmem=2G \ -device pc-dimm,id=dimm-mem1,memdev=mem1 -object \ memory-backend-file,policy=default,mem-path=/...,size=1G,id=mem1 the code in getrampagesize() currently assumes that huge pages are possible since they are enabled for the mem1 object. But since the main RAM is not backed by a huge page filesystem, the guest Linux kernel then crashes very quickly after being started. So in case the we've got "normal" memory without NUMA and without the global "-mem-path" option, we must not announce huge pages to the guest. Since this is likely a mis-configuration by the user, also spill out a message in this case. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt6-3/+241
This adds the ISA 2.06 and later power management instructions (doze, nap, sleep and rvwinkle) and associated wakeup cause testing in LPCR Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Move exception generation code out of lineBenjamin Herrenschmidt1-3/+3
There's no point inlining this, if you hit the exception case you exit anyway, and not inlining saves about 100K of code size (and cache footprint). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: removed '__attribute__((noinline))' from original patch ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Turn a bunch of booleans from int to boolBenjamin Herrenschmidt1-19/+18
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt3-14/+55
Those instructions are only available in hypervisor real mode and allow cache inhibited garded access to devices in that mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Rework generation of priv and inval interruptsBenjamin Herrenschmidt2-399/+310
Recent server processors use the Hypervisor Emulation Assistance interrupt for illegal instructions and *some* type of SPR accesses. Also the code was always generating inval instructions even for priv violations due to setting the wrong flags Finally, the checking for PR/HV was open coded everywhere. This reworks it all, using little helper macros for checking, and adding the HV interrupt (which gets converted back to program check in the slow path of excp_helper.c on CPUs that don't want it). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix generation if ISI/DSI vs. HV modeBenjamin Herrenschmidt1-19/+50
Under some circumstances, we need to direct ISI and DSI interrupts at the hypervisor, turning them into HISI/HDSI, and using different SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and the corresponding VPM bits in LPCR. This moves part of the code into helpers that are fixed to select the right exception type and registers. On pre-P7 processors, LPCR is 0 which provides the old behaviour of directing the interrupts at the supervisor. Thanks to Andrei Warkentin for finding a bug when HV=1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: Merged a fix on POWERPC_EXCP_HDSI fixing the condition on msr_hv, from Andrei Warkentin <andrey.warkentin@gmail.com> ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix POWER7 and POWER8 exception definitionsBenjamin Herrenschmidt2-7/+31
We were initializing unused ones and missing some Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: fix exception model for HV modeBenjamin Herrenschmidt1-89/+45
This properly implements LPES0 handling for HV vs. !HV mode and removes the unsupported LPES1. This has been removed from the specs since ISA v2.07. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: AIL implementation was fixed in commit 5c94b2a5e5ef. This patch only contains the bits of the original patch related to LPES0 handling, adapted commit log. fixed checkpatch.pl errors. ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: define a default LPCR valueBenjamin Herrenschmidt1-0/+14
This allows us to set the appropriate LPCR bits which will be used when fixing the exception model for the HV mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: previous commit 26a7f1291bb5 did not include the LPCR setting as it was not needed at the time, adapted commit log ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix rfi/rfid/hrfi/... emulationBenjamin Herrenschmidt2-31/+24
This reworks emulation of the various "rfi" variants. I removed some masking bits that I couldn't make sense of, the only bit that I am aware we should mask here is POW, the CPU's MSR mask should take care of the rest. This also fixes some problems when running 32-bit userspace under a 64-bit kernel. This patch broke 32bit OpenBIOS when run under a 970 cpu. A fix was proposed here : https://www.coreboot.org/pipermail/openbios/2016-June/009452.html Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: updated the commit log with the reference of the openbios fix ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Remove hunk which disabled rfi on 64-bit CPUS. The change was correct, but we need to fix OpenBIOS before applying it] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22ppc: Improve emulation of THRM registersBenjamin Herrenschmidt3-3/+54
The 75x and 74xx processors have some thermal monitoring SPRs that some OSes such as MacOS do use. Our current "dumb" implementation isn't good enough and will cause some versions of MacOS to hang during boot. This lifts an improved emulation from MacOnLinux and adapts it to qemu, thus fixing the problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fixed typo in comment, a number of minor checkpatch warnings, and a compile failure with CONFIG_USER_ONLY] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22target-ppc: Fix rlwimi, rlwinm, rlwnm againRichard Henderson1-3/+1
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without considering the effect of a mask value that wraps around to the high bits of the word. [dwg: In 2e11b15 this was partially fixed, but an edge case was still incorrect, which this fixes] Signed-off-by: Richard Henderson <rth@twiddle.net> [dwg: Folded with a revert of 2e11b15, an earlier buggy version of this patch which already went upstream] Tested-by: Anton Blanchard <anton@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22ppc64: disable gen_pause() for linux-user modeLaurent Vivier1-1/+3
While trying to install a fedora container with "lxc-create -t fedora -- -I qemu-ppc64" the installation abort with the following error: qemu: fatal: Unknown exception 0x65537. Aborting NIP 0000004000927924 LR 00000040009e325c CTR 0000004000927480 XER 0000000000000000 CPU#0 MSR 9000000102806000 HID0 0000000000000000 HF 9000000002806000 iidx 3 didx 3 TB 00248932 1069155773327487 GPR00 00000040009e325c 00000040007ff800 0000004000aba098 0000000000000000 GPR04 00000040007ff878 0000004000dcb588 0000004000dcb830 0000004000a7a098 GPR08 0000000000000000 0000000000000000 00000040007ff878 0000004000927960 GPR12 0000000022022448 0000004000e2aef0 0000000000000000 0000000000000000 GPR16 0000000000000000 0000000000000000 0000000000000002 0000000000000001 GPR20 0000000000000000 0000000000000000 0000000000000000 0000004000800699 GPR24 0000004000e13320 0000000000000000 0000004000ac9ad8 0000004000ac9ae0 GPR28 0000000000000001 00000000100210a0 0000000000000000 0000000000000038 CR 22022442 [ E E - E E G G E ] RES ffffffffffffffff FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPSCR 0000000000000000 /usr/share/lxc/templates/lxc-fedora: line 487: 26661 Aborted (core dumped) chroot . yum -y --nogpgcheck --installroot /run/install install python rpm yum I've bisected until the commit: commit b68e60e6f0d2865e961a800fb8db96a7fc6494c4 Author: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: Tue May 3 18:03:33 2016 +0200 ppc: Get out of emulation on SMT "OR" ops Otherwise tight loops at smt_low for example, which OPAL does, eat so much CPU that we can't boot a kernel anymore. With that, I can boot 8 CPUs just fine with powernv. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> We can fix that by preventing to send EXCP_HLT in the case of linux-user mode, as the main loop doesn't know how to manage it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-20trace: split out trace events for target-ppc/ directoryDaniel P. Berrange1-0/+5
Move all trace-events for files in the target-ppc/ directory to their own file. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 1466066426-16657-39-git-send-email-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova1-0/+1
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-17spapr: Abstract CPU core device and type specific core devicesBharata B Rao1-0/+28
Add sPAPR specific abastract CPU core device that is based on generic CPU core device. Use this as base type to create sPAPR CPU specific core devices. TODO: - Add core types for other remaining CPU types - Handle CPU model alias correctly Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-17target-ppc: Fix rlwimi, rlwinm, rlwnmRichard Henderson1-21/+52
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without considering the effect of a mask value that wraps around to the high bits of the word. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-17target-ppc: Bug in BookE wait instructionJakub Horak1-1/+1
Fixed bug in code generation for the PowerPC "wait" instruction. It doesn't make sense to store a non-initialized register. Signed-off-by: Jakub Horak <thement@ibawizard.net> [dwg: revised commit message] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-16os-posix: include sys/mman.hPaolo Bonzini1-1/+0
qemu/osdep.h checks whether MAP_ANONYMOUS is defined, but this check is bogus without a previous inclusion of sys/mman.h. Include it in sysemu/os-posix.h and remove it from everywhere else. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth1-0/+3
Make sure that guests can use the PowerISA 2.07 CPU sPAPR compatibility mode when they request it and the target CPU supports it. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth2-4/+13
When using an olderr PowerISA level, all the upper compatibility bits have to be enabled, too. For example when we want to run something in PowerISA 2.05 compatibility mode on POWER8, the bit for 2.06 has to be set beside the bit for 2.05. Additionally, to make sure that we do not set bits that are not supported by the host, we apply a mask with the known-to-be-good bits here, too. Signed-off-by: Thomas Huth <thuth@redhat.com> [dwg: Added some #ifs to fix compile on 32-bit targets] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Provide function to get CPU class of the host CPUThomas Huth2-5/+21
When running with KVM, we might be interested in some details of the host CPU class, too, so provide a function to get the corresponding CPU class. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth3-3/+7
The current pcr_mask values are ambiguous: Should these be the mask that defines valid bits in the PCR register? Or should these rather indicate which compatibility levels are possible? Anyway, POWER6 and POWER7 should certainly not use the same values here. So let's introduce an additional variable "pcr_supported" here which is used to indicate the valid compatibility levels, and use pcr_mask to signal the valid bits in the PCR register. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-2/+0
pc, pci, virtio: new features, cleanups, fixes This includes some infrastructure for ipmi smbios tables. Beginning of acpi hotplug rework by Igor for supporting >255 CPUs. Misc cleanups and fixes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 07 Jun 2016 13:55:22 BST # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: (25 commits) virtio: move bi-endian target support to a single location pc-dimm: introduce realize callback pc-dimm: get memory region from ->get_memory_region() acpi: make bios_linker_loader_add_checksum() API offset based acpi: make bios_linker_loader_add_pointer() API offset based tpm: apci: cleanup TCPA table initialization acpi: cleanup bios_linker_loader_cleanup() acpi: simplify bios_linker API by removing redundant 'table' argument acpi: convert linker from GArray to BIOSLinker structure pc: use AcpiDeviceIfClass.send_event to issue GPE events acpi: extend ACPI interface to provide send_event hook pc: Postpone SMBIOS table installation to post machine init ipmi: rework the fwinfo to be fetched from the interface tests: acpi: update tables with consolidated legacy cpu-hotplug AML pc: acpi: cpuhp-legacy: switch ProcessorID to possible_cpus idx pc: acpi: simplify build_legacy_cpu_hotplug_aml() signature pc: acpi: consolidate legacy CPU hotplug in one file pc: acpi: mark current CPU hotplug functions as legacy pc: acpi: cpu-hotplug: make AML CPU_foo defines local to cpu_hotplug_acpi_table.c pc: acpi: consolidate \GPE._E02 with the rest of CPU hotplug AML ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz1-2/+0
Paolo's recent cpu.h cleanups broke legacy virtio for ppc64 LE guests (and arm BE guests as well, even if I have not verified that). Especially, commit "33c11879fd42 qemu-common: push cpu.h inclusion out of qemu-common.h" has the side-effect of silently hiding the TARGET_IS_BIENDIAN macro from the virtio memory accessors, and thus fully disabling support of endian changing targets. To be sure this cannot happen again, let's gather all the bi-endian bits where they belong in include/hw/virtio/virtio-access.h. The changes in hw/virtio/vhost.c are safe because vhost_needs_vring_endian() is not called on a hot path and non bi-endian targets will return false anyway. While here, also rename TARGET_IS_BIENDIAN to be more precise: it is only for legacy virtio and bi-endian guests. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-07ppc: Do not take exceptions on unknown SPRs in privileged modeBenjamin Herrenschmidt1-2/+9
The architecture specifies that mtspr/mfspr on an unknown SPR number should act as a nop in privileged mode. I haven't removed the warning however as it can be useful for diagnosing. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt3-0/+57
Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix slbia decodeBenjamin Herrenschmidt1-1/+1
Since at least the 2.05 architecture, the slbia instruction takes an IH field in the opcode to provide some control on the effect of the slbia on the ERATs (level-1 TLB). We can safely ignore it as we always flush the whole qemu TLB but we should allow the bits in the decode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix mtmsr decodingBenjamin Herrenschmidt1-1/+1
We had code to handle the L bit in the opcode but we didn't allow it in the decode mask. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt2-2/+5
The PPC_64BX instruction flag is used for a couple of newer instructions currently on POWER8 but our implementation for them works for POWER7 too (and already does the proper checking of what is permitted) with one exception: stq needs to check the ISA version. This fixes the latter and add the instructions to POWER7 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt1-0/+18
We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt4-44/+31
This ports the existing 64-bit mechanism to 32-bit, thus series of 64 tlbie's followed by a sync like some versions of Darwin (ab)use will result in a single flush. We apply a pending flush on any sync instruction though, as Darwin doesn't use tlbsync on non-SMP systems. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processorsBenjamin Herrenschmidt1-0/+8
The processor only uses some bits of the address and invalidates an entire congruence class. Some OSes such as Darwin and HelenOS take advantage of this and occasionally invalidate the entire TLB by just doing a series of 64 consecutive tlbie for example. Our code tries to be too smart here only invalidating a segment congruence class (ie, allowing more address bits to be relevant in the invalidation), this fails miserably on those OSes. Instead don't bother, do like ppc64 and blow the whole tlb when tlbie is executed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Properly tag the translation cache based on MMU modeBenjamin Herrenschmidt1-1/+1
We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). We don't anymore since we have split mmu_idx for instruction and data. However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings. Darwin gets hurt by this problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07target-ppc: fixup bitrot in mmu_helper.c debug statementsMark Cave-Ayland1-14/+24
This fixes compilation of mmu_helper.c when all of the debug #defines at the start of the file are enabled. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: fix hrfid, tlbia and slbia privilegeCédric Le Goater1-3/+3
commit 74693da98894 ('ppc: tlbie, tlbia and tlbisync are HV only') introduced some extra checks on the instruction privilege. slbia was changed wrongly and hrfid, tlbia were forgotten. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt2-4/+8
This helper is only used by the various instructions that can alter MSR and not interrupts. Add a comment to that effect to the interrupt code as well in case somebody wants to change this Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt3-5/+22
We use an env. flag which is set to the initial value of MSR_HVB in the msr_mask. We also adjust the POWER8 mask to set SHV. Also use this to adjust ctx.hv so that it is *set* when the processor doesn't have an HV mode (970 with Apple mode for example), thus enabling hypervisor instructions/SPRs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: ctx.hv used to be defined only for the hypervisor kernel (HV=1|PR=0). It is now defined also when PR=1 and conditions are fixed accordingly. stripped unwanted tabs.] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07target-ppc/fpu_helper: Fix efscmp* instructions handlingTalha Imran1-1/+1
With specification at hand from the reference manual from Freescale http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf , I have found a fix to efscmp* instructions handling in QEMU. efscmp* instructions in QEMU set crD (Condition Register nibble) values as (0b0100 << 2) = 0b10000 (consider the HELPER_SINGLE_SPE_CMP macro which left shifts the value returned by efscmp* handler by 2 bits). A value of 0b10000 is not correct according the to the reference manual. The reference manual expects efscmp* instructions to return a value of 0bx1xx. Please find attached a patch which disables left shifting in HELPER_SINGLE_SPE_CMP macro. This macro is used by efscmp* and efstst* instructions only. efstst* instruction handlers, in turn, call efscmp* handlers too. *Explanation:* Traditionally, each crD (condition register nibble) consist of 4 bits, which is set by comparisons as follows: crD = W X Y Z where W = Less than X = Greater than Y = Equal to However, efscmp* instructions being a special case return a binary result. (efscmpeq will set the crD = 0bx1xx iff when op1 == op2 and 0bx0xx otherwise; i.e. there is no notion of different crD values based on Less than, Greater than and Equal to). This effectively means that crD will store a "Greater than" comparison result iff efscmp* instruction comparison is TRUE. Compiler exploits this feature by checking for "Branch if Less than or Equal to" (ble instruction) OR "Branch if Greater than" (bgt instruction) for Branch if FALSE OR Branch if TRUE respectively after an efscmp* instruction. This can be seen in a assembly code snippet below: 27 if (__real__ x != 3.0f || __imag__ x != 4.0f) 10000498: lwz r10,8(r31) 1000049c: lis r9,16448 100004a0: efscmpeq cr7,r10,r9 100004a4: ble- cr7,0x100004b8 <bar+60> //jump to abort() call 100004a8: lwz r10,12(r31) 100004ac: lis r9,16512 100004b0: efscmpeq cr7,r10,r9 100004b4: bgt- cr7,0x100004bc <bar+64> //skip abort() call 28 abort (); 100004b8: bl 0x10000808 <abort> Signed-off-by: Talha Imran <talha_imran@mentor.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-05target-*: dfilter support for in_asmRichard Henderson1-1/+2
The arm target was handled by 06486077, but other targets were ignored. This handles all the rest which actually support disassembly (that is, skipping moxie and tilegx). Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-05-30ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt1-2/+2
This will enable decoding of hrfid Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: Get out of emulation on SMT "OR" opsBenjamin Herrenschmidt1-3/+18
Otherwise tight loops at smt_low for example, which OPAL does, eat so much CPU that we can't boot a kernel anymore. With that, I can boot 8 CPUs just fine with powernv. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: Fix sign extension issue in mtmsr(d) emulationMichael Neuling1-2/+2
Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: Change 'invalid' bit mask of tlbiel and tlbieBenjamin Herrenschmidt1-2/+4
Otherwise it will trip on the forms used in recent architecture. Ideally, we should have different handlers for different architecture levels but our current implementation of TLB flushing is dumb enough that this will do for now. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: tlbie, tlbia and tlbisync are HV onlyBenjamin Herrenschmidt1-3/+3
Not that anything remotely recent supports tlbia but ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt7-12/+71
On ppc64 especially, we flush the tlb on any slbie or tlbie instruction. However, those instructions often come in bursts of 3 or more (context switch will favor a series of slbie's for example to an slbia if the SLB has less than a certain number of entries in it, and tlbie's can happen in a series, with PAPR, H_BULK_REMOVE can remove up to 4 entries at a time. Doing a tlb_flush() each time is a waste of time. We end up doing a memset of the whole TLB, reloading it for the next instruction, memset'ing again, etc... Those instructions don't have to take effect immediately. For slbie, they can wait for the next context synchronizing event. For tlbie, the next tlbsync. This implements batching by keeping a flag that indicates that we have a TLB in need of flushing. We check it on interrupts, rfi's, isync's and tlbsync and flush the TLB if needed. This reduces the number of tlb_flush() on a boot to a ubuntu installer first dialog screen from roughly 360K down to 36K. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: added a 'CPUPPCState *' variable in h_remove() and h_bulk_remove() ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: removed spurious whitespace change, use 0/1 not true/false consistently, since tlb_need_flush has int type] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: Use split I/D mmu modes to avoid flushes on interruptsBenjamin Herrenschmidt5-25/+63
We rework the way the MMU indices are calculated, providing separate indices for I and D side based on MSR:IR and MSR:DR respectively, and thus no longer need to flush the TLB on context changes. This also adds correct support for HV as a separate address space. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-30ppc: Remove MMU_MODEn_SUFFIX definitionsBenjamin Herrenschmidt1-3/+0
We don't use the resulting accessors and this gets in the way of the split I/D TLB work. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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