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2012-04-15target-ppc: Init dcache and icache size for e500 user modeMeador Inge1-1/+4
commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icache line size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block. This is not correct because instructions like 'dcbz' need the dcache size initialized even for user mode. Signed-off-by: Meador Inge <meadori@codesourcery.com> Cc: Varun Sethi <Varun.Sethi@freescale.com> [AF: Simplify #ifdefs by using cache line size 32 for *-user as before] Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Fix type casts for w64 (uintptr_t)Stefan Weil1-3/+3
This changes nothing for other hosts. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: QOM'ify CPU resetAndreas Färber1-1/+45
Move code from cpu_state_reset() into ppc_cpu_reset(). Reorder #include of helper_regs.h to use it in translate_init.c. Adjust whitespace and add braces. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Start QOM'ifying CPU initAndreas Färber1-0/+9
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: QOM'ify CPUAndreas Färber1-0/+37
Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Add hooks for handling tcg and kvm limitationsDavid Gibson1-16/+35
On target-ppc, our table of CPU types and features encodes the features as found on the hardware, regardless of whether these features are actually usable under TCG or KVM. We already have cases where the information from the cpu table must be fixed up to account for limitations in the emulation method we're using. e.g. TCG does not support the DFP and VSX instructions and KVM needs different numbering of the CPUs in order to tell it the correct thread to core mappings. This patch cleans up these hacks to handle emulation limitations by consolidating them into a pair of functions specifically for the purpose. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [AF: Style and typo fixes, rename new functions and drop ppc_def_t arg] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-07Replace Qemu by QEMU in commentsStefan Weil1-12/+12
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-15ppc: Correctly define POWERPC_INSNS2_DEFAULTMeador Inge1-2/+2
'POWERPC_INSNS2_DEFAULT' was defined incorrectly which was causing the opcode table creation code to erroneously register 'eieio' and 'mbar' for the "default" processor: ** ERROR: opcode 1a already assigned in opcode table 16 *** ERROR: unable to insert opcode [1f-16-1a] *** ERROR initializing PowerPC instruction 0x1f 0x16 0x1a Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15PPC: Add PIR register to POWER7 CPUNathan Whitehorn1-0/+5
The POWER7 emulation is missing the Processor Identification Register, mandatory in recent POWER CPUs, that is required for SMP on at least some operating systems (e.g. FreeBSD) to function properly. This patch copies the existing PIR code from the other CPUs that implement it. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-15PPC64: Add support for ldbrx and stdbrx instructionsThomas Huth1-1/+1
These instructions for loading and storing byte-swapped 64-bit values have been introduced in PowerISA 2.06. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-03-14target-ppc: Don't overuse CPUStateAndreas Färber1-21/+21
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-02PPC: E500: Populate L1CFG0 SPRAlexander Graf1-1/+4
When running Linux on e500 with powersave-nap enabled, Linux tries to read out the L1CFG0 register and calculates some things from it. Passing 0 there ends up in a division by 0, resulting in -1, resulting in badness. So let's populate the L1CFG0 register with reasonable defaults. That way guests aren't completely confused. Reported-by: Shrijeet Mukherjee <shm@cumulusnetworks.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500mc: Enable processor controlAlexander Graf1-1/+1
The e500mc implements Embedded.Processor Control, so enable it and thus enable guests to IPI each other. This makes -smp work with -cpu e500mc. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500: msync is 440 only, e500 has real syncAlexander Graf1-3/+3
The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500mc: add missing IVORs to bitmapAlexander Graf1-1/+5
E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE support too. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: Add IVOR 38-42Alexander Graf1-14/+15
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-01-21PPC: Enable 440EP CPU targetAlexander Graf1-11/+5
Now that we have 440 TLB emulation, we can also support running the 440EP CPU target in system emulation mode. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-01-03PPC: Add description for the Freescale e500mc core.Varun Sethi1-6/+50
This core is found on chips such as p4080, p3041, p2040, and p5020. More needs to be done to make this viable for TCG (such as missing SPRs and instructions), but this suffices to get KVM running with appropriate kernel support. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> [scottwood@freescale.com: tweak some flags] Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-31ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriateDavid Gibson1-3/+17
The CPU state contains two bitmaps, initialized from the CPU spec which describes which instructions are implemented on the CPU. A couple of bits are defined which cover instructions (VSX and DFP) which are not currently implemented in TCG. So far, these are only used to handle the case of -cpu host because a KVM guest can use the instructions when the host CPU supports them. However, it's a mild layering violation to simply not include those bits in the CPU descriptions for those CPUs that do support them, just because we can't handle them in TCG. This patch corrects the situation, so that the instruction bits _are_ shown correctly in the cpu spec table, but are masked out from the cpu state in the non-KVM case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30pseries: Correct vmx/dfp handling in both KVM and TCG casesDavid Gibson1-16/+2
Currently, when KVM is enabled, the pseries machine checks if the host CPU supports VMX, VSX and/or DFP instructions and advertises accordingly in the guest device tree. It does this regardless of what CPU is selected on the command line. On the other hand, when in TCG mode, it never advertises any of these facilities, even basic VMX (Altivec) which is supported in TCG. Now that we have a -cpu host option for ppc, it is fairly straightforward to fix both problems. This patch changes the -cpu host code to override the basic cpu spec derived from the PVR with information queried from the host avout VMX, VSX and DFP capability. The pseries code then uses the instruction availability advertised in the cpu state to set the guest device tree correctly for both the KVM and TCG cases. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30PPC: Disable non-440 CPUs for ppcemb targetAlexander Graf1-0/+24
The sole reason we have the ppcemb target is to support MMUs that have less than the usual 4k possible page size. There are very few of these chips and I don't want to add additional QA and testing burden to everyone to ensure that code still works when TARGET_PAGE_SIZE is not 4k. So this patch disables all CPUs except for MMU_BOOKE capable ones from the ppcemb target. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3David Gibson1-0/+4
This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3. This allows -cpu host to be used on these host cpus. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: First cut implementation of -cpu hostDavid Gibson1-1/+7
For convenience with kvm, x86 allows the user to specify -cpu host on the qemu command line, which means make the guest cpu the same as the host cpu. This patch implements the same option for ppc targets. For now, this just read the host PVR (Processor Version Register) and selects one of our existing CPU specs based on it. This means that the option will not work if the host cpu is not supported by TCG, even if that wouldn't matter for use under kvm. In future, we can extend this in future to override parts of the cpu spec based on information obtained from the host (via /proc/cpuinfo, the host device tree, or explicit KVM calls). That will let us handle cases where the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated CPU. With appropriate annotation of the CPU specs we'll also then be able to use host cpus under kvm even when there isn't a matching full TCG model. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30ppc: Remove broken partial PVR matchingDavid Gibson1-30/+6
The ppc target contains a ppc_find_by_pvr() function, which looks up a CPU spec based on a PVR (that is, based on the value in the target cpu's Processor Version Register). PVR values contain information on both the cpu model (upper 16 bits, usually) and on the precise revision (low 16 bits, usually). ppc_find_by_pvr, as well as making exact PVR matches, attempts to find "close" PVR matches, when we don't have a CPU spec for the exact revision specified. This sounds like a good idea, execpt that the current logic is completely nonsensical. It seems to assume CPU families are subdivided bit by bit in the PVR in a way they just aren't. Specifically, it requires a match on all bits of the specified pvr up to the last non-zero bit. This has the bizarre effect that when the low bits are simply a sequential revision number (a common though not universal pattern), then odd specified revisions must be matched exactly, whereas even specified revisions will also match the next odd revision, likewise for powers of 4, 8 and so forth. To correctly do inexact matching we'd need to re-organize the table of CPU specs to include a mask showing what PVR range the spec is compatible with (similar to the cputable code in the Linux kernel). For now, just remove the bogosity by only permitting exact PVR matches. That at least makes the matching simple and consistent. If we need inexact matching we can add the necessary per-subfamily masks later. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: booke timersFabien Chouteau1-0/+39
While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Gdbstub: handle read of fpscrFabien Chouteau1-2/+1
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson1-1/+22
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-3/+3
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-06-17PPC: move TLBs to their own arraysAlexander Graf1-1/+26
Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-03ppc: Fix compilation for ppc64-softmmuStefan Weil1-6/+6
When QEMU was configured with --enable-debug-tcg, compilation fails in spr_write_booke206_mmucsr0() and in spr_write_booke_pid(). Similar changes are also needed in conditional code which is normally unused. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-14Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno1-80/+202
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: Qdev'ify e500 pci PPC MPC7544DS: Use new TLB helper function PPC: Implement e500 (FSL) MMU PPC: Add another 64 bits to instruction feature mask PPC: Add GS MSR definition PPC: Make MPC8544DS emulation work w/o KVM PPC: Make MPC8544DS obey -cpu switch Fix off-by-one error in sizing pSeries hcall table ppc64: Fix out-of-tree builds kvm: ppc: warn user on PAGE_SIZE mismatch kvm: ppc: detect old headers monitor: add PPC BookE SPRs kvm: ppc: fixes for KVM_SET_SREGS on init ppc64: Don't try to build sPAPR RTAS on Darwin Place pseries vty devices at addresses more similar to existing machines Make pSeries 'model' property more closely resemble real hardware pseries: Increase maximum CPUs to 256
2011-05-12PPC: Implement e500 (FSL) MMUAlexander Graf1-49/+114
Most of the code to support e500 style MMUs is already in place, but we're missing on some of the special TLB0-TLB1 handling code and slightly different TLB modification. This patch adds support for the FSL style MMU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12PPC: Add another 64 bits to instruction feature maskAlexander Graf1-33/+90
To enable quick runtime detection of instruction groups to the currently selected CPU emulation, we have a feature mask of what exactly the respective instruction supports. This feature mask is 64 bits long and we just successfully exceeded those 64 bits. To add more features, we need to think of something. The easiest solution that came to my mind was to simply add another 64 bits that we can also match on. Since the comparison is only done on start of the qemu process to generate an internal opcode calling table, we should be fine on any performance penalties here. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-08Fix typos in comments (instanciation -> instantiation)Stefan Weil1-1/+1
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-04-01Add POWER7 support for ppcDavid Gibson1-0/+107
This adds emulation support for the recent POWER7 cpu to qemu. It's far from perfect - it's missing a number of POWER7 features so far, including any support for VSX or decimal floating point instructions. However, it's close enough to boot a kernel with the POWER7 PVR. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Parse SDR1 on mtspr instead of at translate timeDavid Gibson1-6/+1
On ppc machines with hash table MMUs, the special purpose register SDR1 contains both the base address of the encoded size (hashed) page tables. At present, we interpret the SDR1 value within the address translation path. But because the encodings of the size for 32-bit and 64-bit are different this makes for a confusing branch on the MMU type with a bunch of curly shifts and masks in the middle of the translate path. This patch cleans things up by moving the interpretation on SDR1 into the helper function handling the write to the register. This leaves a simple pre-sanitized base address and mask for the hash table in the CPUState structure which is easier to work with in the translation path. This makes the translation path more readable. It addresses the FIXME comment currently in the mtsdr1 helper, by validating the SDR1 value during interpretation. Finally it opens the way for emulating a pSeries-style partition where the hash table used for translation is not mapped into the guests's RAM. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement missing parts of the logic for the POWER PURRDavid Gibson1-0/+8
The PURR (Processor Utilization Resource Register) is a register found on recent POWER CPUs. The guts of implementing it at least enough to get by are already present in qemu, however some of the helper functions needed to actually wire it up are missing. This patch adds the necessary glue, so that the PURR can be wired up when we implement newer POWER CPU targets which include it. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-02-16Handle icount for powerpc tbl/tbu/decr load and store.Tristan Gingold1-0/+42
Handle option '-icount X' on powerpc targets. Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-1/+1
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-30powerpc: Add a ppc-440x5 Xilinx modelEdgar E. Iglesias1-2/+4
Add a powerpc 440x5 with the model ID on the Xilinx virtex5. Connect the 440x5 to the 40x interrupt logic. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2010-07-19target-ppc: fix power mode checking on 7400/7410Aurelien Jarno1-2/+2
Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC 7400 and 7410 support it.
2010-03-26target-ppc: generic PowerPC TBLDmitry Ilyevsky1-4/+4
Time base SPRs TBL/TBU should be accessible in user/priv modes for reading as specified in POWER ISA documentation. Therefore SPRs permissions were changed in gen_tbl function. Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: simpler definitions for microcontrollers based on e300Thomas Monjalon1-68/+44
No need to alias e300 core for each CPU package. Differences between microcontrollers have to be implemented in a higher layer than translate_init.c Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: add declarations of microcontrollers based on e300Thomas Monjalon1-8/+40
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: better support of e300 CPU coreThomas Monjalon1-2/+8
Declare HID2 register. Use high BATs for e300 (8 instead of 4). Fix index of high BATs registers. Before the fix, IBAT4-7 were overwriting IBAT0-3. Signed-off-by: François Armand <francois.armand@os4i.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-39/+39
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-39/+39
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-16Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plxBlue Swirl1-2/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela1-2/+2
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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