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path: root/target-ppc/translate_init.c
AgeCommit message (Expand)AuthorFilesLines
2013-02-23target-ppc: Split out SO, OV, CA fields from XERRichard Henderson1-2/+2
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
2013-02-16target-ppc: Move TCG initialization to PowerPCCPU initfnAndreas Färber1-5/+4
2013-02-16target-ppc: Update PowerPCCPU to QOM realizefnAndreas Färber1-3/+9
2013-02-11error: Strip trailing '\n' from error string arguments (again)Markus Armbruster1-1/+1
2013-02-01cpu: do not use object_deletePaolo Bonzini1-1/+1
2013-02-01PPC: Unify dcbzl code pathAlexander Graf1-5/+5
2013-01-27cpu: Add model resolution support to CPUClassAndreas Färber1-0/+2
2013-01-25target-ppc: Give a meaningful error if too many threads are specifiedMike Qiu1-0/+12
2013-01-18PPC: Provide zero SVR for -cpu e500mc and e5500Alexander Graf1-2/+2
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber1-4/+6
2013-01-07target-ppc: Slim conversion of model definitions to QOM subclassesAndreas Färber1-107/+238
2013-01-07PPC: Bring EPR support closer to realityAlexander Graf1-6/+1
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini1-2/+2
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-10-29target-ppc: Rework storage of VPA registration stateDavid Gibson1-3/+4
2012-10-29PPC: 440: Emulate DCBR0Alexander Graf1-1/+1
2012-10-05ppc/pseries: Reset VPA registration on CPU resetDavid Gibson1-0/+8
2012-08-15win32: provide separate macros for weak decls and definitionsAnthony Liguori1-2/+2
2012-08-13target-ppc: add implementation of query-cpu-definitions (v2)Anthony Liguori1-0/+26
2012-06-24target-ppc: Fix 2nd parameter for tcg_gen_shri_tlStefan Weil1-1/+1
2012-06-24PPC: BookE: Support 32 and 64 bit wide MAS2Alexander Graf1-1/+18
2012-06-24PPC: Extract SPR dump generation into its own functionAlexander Graf1-12/+18
2012-06-24PPC: Add e5500 CPU targetAlexander Graf1-3/+93
2012-06-24PPC: BookE: Make ivpr selectable by CPU typeAlexander Graf1-4/+5
2012-06-24ppc64: Rudimentary Support for extra page sizes on server CPUsBenjamin Herrenschmidt1-0/+21
2012-06-24ppc: Avoid AREG0 for misc helpersBlue Swirl1-6/+6
2012-06-24ppc: Avoid AREG0 for timebase helpersBlue Swirl1-19/+19
2012-06-24ppc: Avoid AREG0 for MMU etc. helpersBlue Swirl1-12/+12
2012-05-01PPC: Fix up e500 cache size settingAlexander Graf1-12/+14
2012-04-15target-ppc: Init dcache and icache size for e500 user modeMeador Inge1-1/+4
2012-04-15target-ppc: Fix type casts for w64 (uintptr_t)Stefan Weil1-3/+3
2012-04-15target-ppc: QOM'ify CPU resetAndreas Färber1-1/+45
2012-04-15target-ppc: Start QOM'ifying CPU initAndreas Färber1-0/+9
2012-04-15target-ppc: QOM'ify CPUAndreas Färber1-0/+37
2012-04-15target-ppc: Add hooks for handling tcg and kvm limitationsDavid Gibson1-16/+35
2012-04-07Replace Qemu by QEMU in commentsStefan Weil1-12/+12
2012-03-15ppc: Correctly define POWERPC_INSNS2_DEFAULTMeador Inge1-2/+2
2012-03-15PPC: Add PIR register to POWER7 CPUNathan Whitehorn1-0/+5
2012-03-15PPC64: Add support for ldbrx and stdbrx instructionsThomas Huth1-1/+1
2012-03-14target-ppc: Don't overuse CPUStateAndreas Färber1-21/+21
2012-02-02PPC: E500: Populate L1CFG0 SPRAlexander Graf1-1/+4
2012-02-02PPC: e500mc: Enable processor controlAlexander Graf1-1/+1
2012-02-02PPC: e500: msync is 440 only, e500 has real syncAlexander Graf1-3/+3
2012-02-02PPC: e500mc: add missing IVORs to bitmapAlexander Graf1-1/+5
2012-02-02PPC: Add IVOR 38-42Alexander Graf1-14/+15
2012-01-21PPC: Enable 440EP CPU targetAlexander Graf1-11/+5
2012-01-03PPC: Add description for the Freescale e500mc core.Varun Sethi1-6/+50
2011-10-31ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriateDavid Gibson1-3/+17
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