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path: root/target-ppc/translate_init.c
AgeCommit message (Expand)AuthorFilesLines
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-2/+0
2009-02-03Add calls to initialize VSCR on appropriate machinesaurel321-0/+22
2009-01-24target-ppc: Add SPE register read/write using XMLaurel321-0/+50
2009-01-24target-ppc: Add Altivec register read/write using XMLaurel321-0/+50
2009-01-24target-ppc: Add float register read/write using XMLaurel321-0/+32
2009-01-24target-ppc: Include gdbstub.haurel321-0/+1
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-3/+3
2008-12-11target-ppc: rework exception codeaurel321-3/+3
2008-12-07target-ppc: convert SPR accesses to TCGaurel321-132/+177
2008-11-16Attached patch fixes a series of this warningblueswir11-1/+1
2008-10-21target-ppc: Convert XER accesses to TCGaurel321-2/+2
2008-09-20Suppress gcc 4.x -Wpointer-sign (included in -Wall) warningsblueswir11-9/+9
2008-09-14ppc: Convert ctr, lr moves to TCGaurel321-4/+4
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-2/+0
2007-12-10Fix PowerPC 74xx definitions.j_mayer1-47/+225
2007-11-21Fix PowerPC 7xx definitions.j_mayer1-132/+612
2007-11-19Remove shared macro used to define PowerPC implementations instructions sets:j_mayer1-172/+480
2007-11-19PowerPC 620 MMU do not have the same exact behavior as standardj_mayer1-3/+6
2007-11-19New PowerPC CPU flag to define the decrementer and time-base source clock.j_mayer1-39/+67
2007-11-17Improve PowerPC instructions set dump.j_mayer1-6/+44
2007-11-17Add definitions for Freescale PowerPC implementations,j_mayer1-1259/+2850
2007-11-17Define Freescale cores specific MMU model, exceptions and input bus.j_mayer1-4/+13
2007-11-17A little more granularity in PowerPC instructions definition is neededj_mayer1-21/+25
2007-11-17Make the PowerPC MMU model, exception model and input bus modelj_mayer1-4/+3
2007-11-17Always make all PowerPC exception definitions visible.j_mayer1-2/+0
2007-11-14Reorganize PowerPC instructions categories, add icbi separate case.j_mayer1-4/+6
2007-11-12Add PVR and SPR definition for most embedded PowerPC from Freescale.j_mayer1-59/+309
2007-11-10Allow selection of PowerPC CPU giving a PVR.j_mayer1-371/+420
2007-11-10added cpu_model parameter to cpu_init()bellard1-21/+11
2007-11-04PowerPC 601 need specific callbacks for its BATs setup.j_mayer1-1/+10
2007-11-03Fix PowerPC high BATs access: BAT number was incorrect.j_mayer1-3/+3
2007-11-03PowerPC MMU and exception fixes:j_mayer1-31/+31
2007-10-25Implement power-management for all defined PowerPC CPUs.j_mayer1-7/+172
2007-10-25Allow selection of all defined PowerPC 74xx (aka G4) CPUs.j_mayer1-36/+0
2007-10-14There is no need of a specific MMU model for PowerPC 601.j_mayer1-4/+1
2007-10-08Remove synonymous in PowerPC MSR bits definitions.j_mayer1-39/+171
2007-10-08Real-mode only PowerPC 40x do not have any TLBs.j_mayer1-1/+0
2007-10-08Implement exception prefix feature for PowerPC 601.j_mayer1-1/+1
2007-10-08Add missing exception vectors for PowerPC 7x5.j_mayer1-1/+27
2007-10-07Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).j_mayer1-18/+9
2007-10-07Reorganize the CPUPPCState structure to group features.j_mayer1-3/+46
2007-10-07Add MSR bits signification per PowerPC implementation flags (to be continued).j_mayer1-0/+42
2007-10-05Full implementation of PowerPC 64 MMU, just missing support for 1 TBj_mayer1-22/+65
2007-10-05Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.j_mayer1-2/+2
2007-10-05PowerPC hardware reset vector is now considered as part of the exception model.j_mayer1-132/+30
2007-10-04More cache tuning fixes:j_mayer1-2/+22
2007-10-04Make PowerPC cache line size implementation dependant.j_mayer1-10/+236
2007-10-03HID0 is a write-clear register on 970 (DBSR).j_mayer1-3/+3
2007-10-03We never have to export ppc_set_irq.j_mayer1-9/+17
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