aboutsummaryrefslogtreecommitdiff
path: root/target-ppc/translate_init.c
AgeCommit message (Expand)AuthorFilesLines
2016-09-27linux-user: remove #define smp_{cores, threads}Marc-André Lureau1-1/+2
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt1-2/+0
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania1-33/+94
2016-09-07target-ppc: Introduce POWER ISA 3.0 flagNikunj A Dadhania1-1/+1
2016-09-07target-ppc: Introduce Power9 familyAneesh Kumar K.V1-1/+85
2016-08-10ppc: Introduce a function to look up CPU alias stringsThomas Huth1-0/+13
2016-07-25target-ppc: add PPC_MFTB flag to e500mc and e5500Michael Walle1-2/+2
2016-07-18ppc: abort if compat property contains an unknown valueGreg Kurz1-2/+2
2016-07-12Use #include "..." for our own headers, <...> for othersMarkus Armbruster1-1/+1
2016-07-05ppc/hash64: Add proper real mode translation supportBenjamin Herrenschmidt1-1/+13
2016-07-05ppc: simplify max_smt initialization in ppc_cpu_realizefn()Greg Kurz1-1/+1
2016-07-01ppc: Fix 64K pages support in full emulationBenjamin Herrenschmidt1-3/+19
2016-07-01ppc: LPCR is a HV resourceBenjamin Herrenschmidt1-4/+5
2016-07-01ppc: Initial HDEC supportBenjamin Herrenschmidt1-0/+30
2016-07-01ppc: Use a helper to filter writes to LPCRBenjamin Herrenschmidt1-19/+37
2016-07-01ppc: Add a bunch of hypervisor SPRs to Book3sBenjamin Herrenschmidt1-3/+116
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt1-2/+90
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt1-2/+4
2016-06-23ppc: Fix POWER7 and POWER8 exception definitionsBenjamin Herrenschmidt1-6/+21
2016-06-23ppc: define a default LPCR valueBenjamin Herrenschmidt1-0/+14
2016-06-22ppc: Improve emulation of THRM registersBenjamin Herrenschmidt1-3/+12
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth1-0/+3
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth1-4/+11
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth1-2/+4
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt1-1/+1
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt1-0/+18
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt1-4/+15
2016-05-30ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt1-2/+2
2016-05-27PPC/KVM: early validation of vcpu idGreg Kurz1-0/+8
2016-05-19ppc: use PowerPCCPU instead of CPUPPCStatePaolo Bonzini1-54/+38
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater1-1/+1
2016-03-24ppc: move POWER8 Book4 regs in their own routineCédric Le Goater1-0/+8
2016-03-24ppc: A couple more dummy POWER8 Book4 regsBenjamin Herrenschmidt1-0/+12
2016-03-24ppc: Add dummy CIABR SPRBenjamin Herrenschmidt1-0/+5
2016-03-24ppc: Add POWER8 IAMR registerBenjamin Herrenschmidt1-2/+39
2016-03-24ppc: Fix writing to AMR/UAMORBenjamin Herrenschmidt1-15/+59
2016-03-24ppc: Initialize AMOR in PAPR modeBenjamin Herrenschmidt1-0/+4
2016-03-24ppc: Add dummy SPR_IC for POWER8Benjamin Herrenschmidt1-0/+12
2016-03-24ppc: Create cpu_ppc_set_papr() helperBenjamin Herrenschmidt1-1/+22
2016-03-24ppc: Add a bunch of hypervisor SPRs to Book3sBenjamin Herrenschmidt1-0/+21
2016-03-24ppc: Add macros to register hypervisor mode SPRsBenjamin Herrenschmidt1-4/+31
2016-03-24ppc64: set MSR_SF bitLaurent Vivier1-1/+1
2016-03-16target-ppc: Add PVR for POWER8NVL processorAlexey Kardashevskiy1-0/+3
2016-03-16ppc: Add a few more P8 PMU SPRsBenjamin Herrenschmidt1-0/+28
2016-03-16ppc: Fix migration of the TAR SPRThomas Huth1-4/+4
2016-03-16ppc: Define the PSPB register on POWER8Thomas Huth1-0/+9
2016-02-08qom: Swap 'name' next to visitor in ObjectPropertyAccessorEric Blake1-4/+4
2016-02-08qapi: Swap visit_* arguments for consistent 'name' placementEric Blake1-2/+2
2016-01-30target-ppc: Allow more page sizes for POWER7 & POWER8 in TCGDavid Gibson1-0/+32
2016-01-30target-ppc: gdbstub: Add VSX supportAnton Blanchard1-0/+24
generated by cgit v1.1 at 2024-12-25 13:27:57 +0000