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2016-09-07ppc: Don't generate dead code on unconditional branchesBenjamin Herrenschmidt1-5/+9
We are always generating the "else" case of the condition even when generating an unconditional branch that will never hit it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt1-20/+20
Also while at it, group the #include statements in translate.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add extswsli[.] instructionNikunj A Dadhania1-0/+28
extswsli : Extend Sign Word & Shift Left Immediate Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: implement branch-less divd[o][.]Nikunj A Dadhania1-22/+26
Similar to divw, implement branch-less divd. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: implement branch-less divw[o][.]Nikunj A Dadhania1-25/+23
While implementing modulo instructions figured out that the implementation uses many branches. Change the logic to achieve the branch-less code. Undefined value is set to dividend in case of invalid input. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: load/store multiple and string insns don't do LEBenjamin Herrenschmidt1-0/+29
Just generate an alignment interrupt Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Use a helper to generate "LE unsupported" alignment interruptsBenjamin Herrenschmidt1-3/+8
Some operations aren't allowed in LE mode, use a helper rather than open coding the exception generation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't set access_type on all load/stores on hash64Benjamin Herrenschmidt1-1/+3
We don't use it so let's not generate the updates. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Fix CFAR updatesBenjamin Herrenschmidt1-4/+4
We were one instruction off Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Speed up dcbzBenjamin Herrenschmidt1-7/+4
Use tlb_vaddr_to_host to do a fast path single translate for the whole cache line. Also make the reservation check match the entire range. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Handle unconditional (always/never) traps at translation timeBenjamin Herrenschmidt1-6/+43
We don't need to call a helper for trap always and trap never which are used by Linux under some circumstances. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Don't generate the helper call when trapping always Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make alignment exceptions suck lessBenjamin Herrenschmidt1-1/+1
The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in dcbz and lscbxBenjamin Herrenschmidt1-4/+0
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP if not taking alignment exceptionsBenjamin Herrenschmidt1-2/+1
Move the NIP update to after the conditional branch so that we don't do it if we aren't going to take the alignment exception Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt1-8/+0
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP BookE 2.06 tlbweBenjamin Herrenschmidt1-1/+0
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt1-7/+0
This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt1-12/+0
This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt1-25/+35
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt1-6/+0
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt1-10/+8
Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean this all up by always having the nip already set to the right instruction when taking the fault. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fix trivial checkpatch warning] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt1-991/+3
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt1-1065/+3
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt1-363/+2
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt1-1326/+2
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt1-1201/+4
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania1-21/+61
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Trivial checkpatch fixup] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania1-0/+25
maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the higher dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania1-0/+14
maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add setb instructionVivek Andrew Sha1-0/+22
The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania1-0/+12
Search a byte in the stream of 8bytes provided in the register Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania1-0/+11
Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das1-0/+10
Add ISA3.0 Count trailing zeros double word Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> [ added ISA300 flag ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo dword operationsNikunj A Dadhania1-0/+48
Adding following instructions for ISA3.0 support modud: Modulo Unsigned Dword modsd: Modulo Signed Dword Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo word operationsNikunj A Dadhania1-0/+48
Adding following instructions: moduw: Modulo Unsigned Word modsw: Modulo Signed Word Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmprb instructionNikunj A Dadhania1-0/+39
ISA 3.0 Compare Ranged Byte instruction useful for isupper/islower/isaplha kind of operation. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: adding addpcis instructionNikunj A Dadhania1-0/+26
ISA 3.0 instruction for adding immediate value shifted with next instruction address and return the result in the target register. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-01target-ppc: gen_pause for instructions: yield, mdoio, mdoom, misoAaron Larson1-7/+8
Call gen_pause for all "or rx,rx,rx" encodings other nop. This provides a reasonable implementation for yield, and a better approximation for mdoio, mdoom, and miso. The choice to pause for all encodings !=0 leverages the PowerISA admonition that the reserved encodings might change program priority, providing a slight "future proofing". Signed-off-by: Aaron Larson <alarson@ddci.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-01ppc: Print HSRR0/HSRR1 in "info registers"Benjamin Herrenschmidt1-0/+7
They are generally useful when debugging HV mode stuff Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt1-0/+66
This adds the ISA 2.06 and later power management instructions (doze, nap, sleep and rvwinkle) and associated wakeup cause testing in LPCR Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Move exception generation code out of lineBenjamin Herrenschmidt1-3/+3
There's no point inlining this, if you hit the exception case you exit anyway, and not inlining saves about 100K of code size (and cache footprint). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: removed '__attribute__((noinline))' from original patch ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Turn a bunch of booleans from int to boolBenjamin Herrenschmidt1-19/+18
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt1-11/+48
Those instructions are only available in hypervisor real mode and allow cache inhibited garded access to devices in that mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Rework generation of priv and inval interruptsBenjamin Herrenschmidt1-399/+291
Recent server processors use the Hypervisor Emulation Assistance interrupt for illegal instructions and *some* type of SPR accesses. Also the code was always generating inval instructions even for priv violations due to setting the wrong flags Finally, the checking for PR/HV was open coded everywhere. This reworks it all, using little helper macros for checking, and adding the HV interrupt (which gets converted back to program check in the slow path of excp_helper.c on CPUs that don't want it). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Fix rfi/rfid/hrfi/... emulationBenjamin Herrenschmidt1-0/+4
This reworks emulation of the various "rfi" variants. I removed some masking bits that I couldn't make sense of, the only bit that I am aware we should mask here is POW, the CPU's MSR mask should take care of the rest. This also fixes some problems when running 32-bit userspace under a 64-bit kernel. This patch broke 32bit OpenBIOS when run under a 970 cpu. A fix was proposed here : https://www.coreboot.org/pipermail/openbios/2016-June/009452.html Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: updated the commit log with the reference of the openbios fix ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Remove hunk which disabled rfi on 64-bit CPUS. The change was correct, but we need to fix OpenBIOS before applying it] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22target-ppc: Fix rlwimi, rlwinm, rlwnm againRichard Henderson1-3/+1
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without considering the effect of a mask value that wraps around to the high bits of the word. [dwg: In 2e11b15 this was partially fixed, but an edge case was still incorrect, which this fixes] Signed-off-by: Richard Henderson <rth@twiddle.net> [dwg: Folded with a revert of 2e11b15, an earlier buggy version of this patch which already went upstream] Tested-by: Anton Blanchard <anton@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-22ppc64: disable gen_pause() for linux-user modeLaurent Vivier1-1/+3
While trying to install a fedora container with "lxc-create -t fedora -- -I qemu-ppc64" the installation abort with the following error: qemu: fatal: Unknown exception 0x65537. Aborting NIP 0000004000927924 LR 00000040009e325c CTR 0000004000927480 XER 0000000000000000 CPU#0 MSR 9000000102806000 HID0 0000000000000000 HF 9000000002806000 iidx 3 didx 3 TB 00248932 1069155773327487 GPR00 00000040009e325c 00000040007ff800 0000004000aba098 0000000000000000 GPR04 00000040007ff878 0000004000dcb588 0000004000dcb830 0000004000a7a098 GPR08 0000000000000000 0000000000000000 00000040007ff878 0000004000927960 GPR12 0000000022022448 0000004000e2aef0 0000000000000000 0000000000000000 GPR16 0000000000000000 0000000000000000 0000000000000002 0000000000000001 GPR20 0000000000000000 0000000000000000 0000000000000000 0000004000800699 GPR24 0000004000e13320 0000000000000000 0000004000ac9ad8 0000004000ac9ae0 GPR28 0000000000000001 00000000100210a0 0000000000000000 0000000000000038 CR 22022442 [ E E - E E G G E ] RES ffffffffffffffff FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000 FPSCR 0000000000000000 /usr/share/lxc/templates/lxc-fedora: line 487: 26661 Aborted (core dumped) chroot . yum -y --nogpgcheck --installroot /run/install install python rpm yum I've bisected until the commit: commit b68e60e6f0d2865e961a800fb8db96a7fc6494c4 Author: Benjamin Herrenschmidt <benh@kernel.crashing.org> Date: Tue May 3 18:03:33 2016 +0200 ppc: Get out of emulation on SMT "OR" ops Otherwise tight loops at smt_low for example, which OPAL does, eat so much CPU that we can't boot a kernel anymore. With that, I can boot 8 CPUs just fine with powernv. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> We can fix that by preventing to send EXCP_HLT in the case of linux-user mode, as the main loop doesn't know how to manage it. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova1-0/+1
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-17target-ppc: Fix rlwimi, rlwinm, rlwnmRichard Henderson1-21/+52
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without considering the effect of a mask value that wraps around to the high bits of the word. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-17target-ppc: Bug in BookE wait instructionJakub Horak1-1/+1
Fixed bug in code generation for the PowerPC "wait" instruction. It doesn't make sense to store a non-initialized register. Signed-off-by: Jakub Horak <thement@ibawizard.net> [dwg: revised commit message] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>