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path: root/target-ppc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2016-09-07ppc: Don't update NIP if not taking alignment exceptionsBenjamin Herrenschmidt1-2/+1
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt1-8/+0
2016-09-07ppc: Don't update NIP BookE 2.06 tlbweBenjamin Herrenschmidt1-1/+0
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt1-7/+0
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt1-12/+0
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt1-25/+35
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt1-6/+0
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt1-10/+8
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt1-991/+3
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt1-1065/+3
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt1-363/+2
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt1-1326/+2
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt1-1201/+4
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania1-21/+61
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania1-0/+25
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania1-0/+14
2016-09-07target-ppc: add setb instructionVivek Andrew Sha1-0/+22
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania1-0/+12
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania1-0/+11
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das1-0/+10
2016-09-07target-ppc: add modulo dword operationsNikunj A Dadhania1-0/+48
2016-09-07target-ppc: add modulo word operationsNikunj A Dadhania1-0/+48
2016-09-07target-ppc: add cmprb instructionNikunj A Dadhania1-0/+39
2016-09-07target-ppc: adding addpcis instructionNikunj A Dadhania1-0/+26
2016-07-01target-ppc: gen_pause for instructions: yield, mdoio, mdoom, misoAaron Larson1-7/+8
2016-07-01ppc: Print HSRR0/HSRR1 in "info registers"Benjamin Herrenschmidt1-0/+7
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt1-0/+66
2016-06-23ppc: Move exception generation code out of lineBenjamin Herrenschmidt1-3/+3
2016-06-23ppc: Turn a bunch of booleans from int to boolBenjamin Herrenschmidt1-19/+18
2016-06-23ppc: Add real mode CI load/store instructions for P7 and P8Benjamin Herrenschmidt1-11/+48
2016-06-23ppc: Rework generation of priv and inval interruptsBenjamin Herrenschmidt1-399/+291
2016-06-23ppc: Fix rfi/rfid/hrfi/... emulationBenjamin Herrenschmidt1-0/+4
2016-06-22target-ppc: Fix rlwimi, rlwinm, rlwnm againRichard Henderson1-3/+1
2016-06-22ppc64: disable gen_pause() for linux-user modeLaurent Vivier1-1/+3
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova1-0/+1
2016-06-17target-ppc: Fix rlwimi, rlwinm, rlwnmRichard Henderson1-21/+52
2016-06-17target-ppc: Bug in BookE wait instructionJakub Horak1-1/+1
2016-06-07ppc: Do not take exceptions on unknown SPRs in privileged modeBenjamin Herrenschmidt1-2/+9
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt1-0/+26
2016-06-07ppc: Fix slbia decodeBenjamin Herrenschmidt1-1/+1
2016-06-07ppc: Fix mtmsr decodingBenjamin Herrenschmidt1-1/+1
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt1-1/+4
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt1-6/+21
2016-06-07ppc: fix hrfid, tlbia and slbia privilegeCédric Le Goater1-3/+3
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt1-1/+3
2016-06-05target-*: dfilter support for in_asmRichard Henderson1-1/+2
2016-05-30ppc: Get out of emulation on SMT "OR" opsBenjamin Herrenschmidt1-3/+18
2016-05-30ppc: Fix sign extension issue in mtmsr(d) emulationMichael Neuling1-2/+2
2016-05-30ppc: Change 'invalid' bit mask of tlbiel and tlbieBenjamin Herrenschmidt1-2/+4
2016-05-30ppc: tlbie, tlbia and tlbisync are HV onlyBenjamin Herrenschmidt1-3/+3
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