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path: root/target-ppc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2016-02-17target-ppc: Include missing MMU models for SDR1 in info registersDavid Gibson1-0/+2
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson1-22/+22
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini1-0/+1
2016-02-01target-ppc: mcrfs should always update FEX/VX and only clear exception bitsJames Clarke1-4/+17
2016-01-30target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()David Gibson1-1/+1
2016-01-29ppc: Clean up includesPeter Maydell1-0/+1
2015-12-17ppc: cleanup loggingPaolo Bonzini1-13/+9
2015-12-17qemu-log: introduce qemu_log_separatePaolo Bonzini1-16/+24
2015-11-12PPC: Allow Rc bit to be set on mtsprAlexander Graf1-1/+1
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-0/+5
2015-10-23ppc: Add mmu_model defines for arch 2.03 and 2.07Benjamin Herrenschmidt1-2/+2
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-35/+5
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+3
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-1/+5
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-9/+5
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-3/+2
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-20target-ppc: fix xscmpodp and xscmpudp decodingAurelien Jarno1-2/+9
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-64/+59
2015-03-09display cpu id dump stateTristan Gingold1-2/+3
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-6/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-01-10Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' int...Peter Maydell1-61/+210
2015-01-07target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLYPeter Maydell1-0/+5
2015-01-07target-ppc: Introduce Privileged TM NoopsTom Musta1-0/+38
2015-01-07target-ppc: Introduce tcheckTom Musta1-0/+17
2015-01-07target-ppc: Introduce TM NoopsTom Musta1-0/+38
2015-01-07target-ppc: Introduce tbeginTom Musta1-0/+12
2015-01-07target-ppc: Introduce tm_enabled Bit to CPU StateTom Musta1-0/+8
2015-01-07target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta1-7/+1
2015-01-07target-ppc: Eliminate set_fprf Argument From gen_compute_fprfTom Musta1-15/+23
2015-01-07target-ppc: Fully Migrate to gen_set_cr1_from_fpscrTom Musta1-22/+33
2015-01-07target-ppc: mffs. Should Set CR1 from FPSCR BitsTom Musta1-1/+3
2015-01-07target-ppc: Fix Floating Point Move Instructions That Set CR1Tom Musta1-20/+30
2015-01-07target-ppc: Load/Store Vector Element Storage AlignmentTom Musta1-8/+14
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-12-23target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini1-5/+5
2014-11-20target-ppc: Altivec's mtvscr Decodes Wrong RegisterTom Musta1-1/+1
2014-11-04target-ppc: Fix Altivec Round OpcodesTom Musta1-6/+6
2014-11-04ppc: do not look at the MMU index to detect PR/HV modePaolo Bonzini1-88/+77
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard1-10/+6
2014-11-04ppc: compute mask from BI using right shiftPaolo Bonzini1-3/+3
2014-11-04ppc: rename gen_set_cr6_from_fpscrPaolo Bonzini1-7/+7
2014-09-08target-ppc: Implement mulldo with TCGTom Musta1-2/+14
2014-09-08target-ppc: Clean up mullwoTom Musta1-8/+3
2014-09-08target-ppc: Clean Up mullwTom Musta1-3/+2
2014-09-08target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta1-22/+34
2014-09-08target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta1-0/+6
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