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path: root/target-ppc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2016-10-28ppc: Fix single step with gdb stubBenjamin Herrenschmidt1-1/+1
2016-10-28target-ppc: implement xxbr[qdwh] instructionNikunj A Dadhania1-0/+32
2016-10-05target-ppc: fix invalid mask - cmpl, bctarAvinesh Kumar1-2/+2
2016-09-23target-ppc: tlbie/tlbivax should have global effectNikunj A Dadhania1-0/+6
2016-09-23target-ppc: add flag in check_tlb_flush()Nikunj A Dadhania1-10/+13
2016-09-23target-ppc: implement darn instructionRavi Bangoria1-0/+20
2016-09-23target-ppc: add stxsi[bh]x instructionNikunj A Dadhania1-0/+2
2016-09-23target-ppc: add lxsi[bw]zx instructionNikunj A Dadhania1-0/+2
2016-09-23target-ppc: add xxspltib instructionNikunj A Dadhania1-0/+2
2016-09-23target-ppc: consolidate store conditionalNikunj A Dadhania1-34/+24
2016-09-23target-ppc: move out stqcx impementationNikunj A Dadhania1-22/+47
2016-09-23target-ppc: consolidate load with reservationNikunj A Dadhania1-11/+11
2016-09-23target-ppc: convert st[16,32,64]r to use new macroNikunj A Dadhania1-22/+10
2016-09-23target-ppc: convert st64 to use new macroNikunj A Dadhania1-21/+16
2016-09-23target-ppc: consolidate store operationsNikunj A Dadhania1-19/+16
2016-09-23target-ppc: convert ld[16,32,64]ur to use new macroNikunj A Dadhania1-17/+10
2016-09-23target-ppc: convert ld64 to use new macroNikunj A Dadhania1-22/+17
2016-09-23target-ppc: consolidate load operationsNikunj A Dadhania1-38/+20
2016-09-23target-ppc: add vector insert instructionsRajalakshmi Srinivasaraghavan1-0/+2
2016-09-23ppc: restrict the use of the rfi instructionBenjamin Herrenschmidt1-3/+6
2016-09-07ppc: Don't generate dead code on unconditional branchesBenjamin Herrenschmidt1-5/+9
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt1-20/+20
2016-09-07target-ppc: add extswsli[.] instructionNikunj A Dadhania1-0/+28
2016-09-07target-ppc: implement branch-less divd[o][.]Nikunj A Dadhania1-22/+26
2016-09-07target-ppc: implement branch-less divw[o][.]Nikunj A Dadhania1-25/+23
2016-09-07ppc: load/store multiple and string insns don't do LEBenjamin Herrenschmidt1-0/+29
2016-09-07ppc: Use a helper to generate "LE unsupported" alignment interruptsBenjamin Herrenschmidt1-3/+8
2016-09-07ppc: Don't set access_type on all load/stores on hash64Benjamin Herrenschmidt1-1/+3
2016-09-07ppc: Fix CFAR updatesBenjamin Herrenschmidt1-4/+4
2016-09-07ppc: Speed up dcbzBenjamin Herrenschmidt1-7/+4
2016-09-07ppc: Handle unconditional (always/never) traps at translation timeBenjamin Herrenschmidt1-6/+43
2016-09-07ppc: Make alignment exceptions suck lessBenjamin Herrenschmidt1-1/+1
2016-09-07ppc: Don't update NIP in dcbz and lscbxBenjamin Herrenschmidt1-4/+0
2016-09-07ppc: Don't update NIP if not taking alignment exceptionsBenjamin Herrenschmidt1-2/+1
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt1-8/+0
2016-09-07ppc: Don't update NIP BookE 2.06 tlbweBenjamin Herrenschmidt1-1/+0
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt1-7/+0
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt1-12/+0
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt1-25/+35
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt1-6/+0
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt1-10/+8
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt1-991/+3
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt1-1065/+3
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt1-363/+2
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt1-1326/+2
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt1-1201/+4
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania1-21/+61
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania1-0/+25
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania1-0/+14
2016-09-07target-ppc: add setb instructionVivek Andrew Sha1-0/+22
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