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Author
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Lines
2016-05-30
ppc: Fix sign extension issue in mtmsr(d) emulation
Michael Neuling
1
-2
/
+2
2016-05-30
ppc: Change 'invalid' bit mask of tlbiel and tlbie
Benjamin Herrenschmidt
1
-2
/
+4
2016-05-30
ppc: tlbie, tlbia and tlbisync are HV only
Benjamin Herrenschmidt
1
-3
/
+3
2016-05-30
ppc: Do some batching of TCG tlb flushes
Benjamin Herrenschmidt
1
-3
/
+36
2016-05-30
ppc: Use split I/D mmu modes to avoid flushes on interrupts
Benjamin Herrenschmidt
1
-3
/
+4
2016-05-27
target-ppc: Cleanups to rldinm, rldnm, rldimi
Richard Henderson
1
-45
/
+46
2016-05-27
target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate
Richard Henderson
1
-102
/
+70
2016-05-27
target-ppc: Use movcond in isel
Richard Henderson
1
-18
/
+11
2016-05-19
cpu: move exec-all.h inclusion out of cpu.h
Paolo Bonzini
1
-0
/
+1
2016-05-12
tcg: Allow goto_tb to any target PC in user mode
Sergey Fedorov
1
-5
/
+15
2016-04-18
ppc: Fix the range check in the LSWI instruction
Thomas Huth
1
-4
/
+2
2016-03-24
ppc: Add macros to register hypervisor mode SPRs
Benjamin Herrenschmidt
1
-10
/
+16
2016-03-01
tcg: Add type for vCPU pointers
LluĂs Vilanova
1
-1
/
+1
2016-02-17
target-ppc: Include missing MMU models for SDR1 in info registers
David Gibson
1
-0
/
+2
2016-02-09
tcg: Change tcg_global_mem_new_* to take a TCGv_ptr
Richard Henderson
1
-22
/
+22
2016-02-03
log: do not unnecessarily include qom/cpu.h
Paolo Bonzini
1
-0
/
+1
2016-02-01
target-ppc: mcrfs should always update FEX/VX and only clear exception bits
James Clarke
1
-4
/
+17
2016-01-30
target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
David Gibson
1
-1
/
+1
2016-01-29
ppc: Clean up includes
Peter Maydell
1
-0
/
+1
2015-12-17
ppc: cleanup logging
Paolo Bonzini
1
-13
/
+9
2015-12-17
qemu-log: introduce qemu_log_separate
Paolo Bonzini
1
-16
/
+24
2015-11-12
PPC: Allow Rc bit to be set on mtspr
Alexander Graf
1
-1
/
+1
2015-10-28
target-*: Advance pc after recognizing a breakpoint
Richard Henderson
1
-0
/
+5
2015-10-23
ppc: Add mmu_model defines for arch 2.03 and 2.07
Benjamin Herrenschmidt
1
-2
/
+2
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
1
-35
/
+5
2015-10-07
tcg: Pass data argument to restore_state_to_opc
Richard Henderson
1
-2
/
+3
2015-10-07
tcg: Add TCG_MAX_INSNS
Richard Henderson
1
-1
/
+5
2015-10-07
target-*: Introduce and use cpu_breakpoint_test
Richard Henderson
1
-9
/
+5
2015-10-07
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
1
-2
/
+2
2015-10-07
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
1
-3
/
+2
2015-10-07
tcg: Rename debug_insn_start to insn_start
Richard Henderson
1
-1
/
+1
2015-09-20
target-ppc: fix xscmpodp and xscmpudp decoding
Aurelien Jarno
1
-2
/
+9
2015-06-22
disas: Remove uses of CPU env
Peter Crosthwaite
1
-1
/
+1
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
1
-64
/
+59
2015-03-09
display cpu id dump state
Tristan Gingold
1
-2
/
+3
2015-02-12
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
1
-6
/
+3
2015-02-12
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
1
-1
/
+1
2015-01-10
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' int...
Peter Maydell
1
-61
/
+210
2015-01-07
target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY
Peter Maydell
1
-0
/
+5
2015-01-07
target-ppc: Introduce Privileged TM Noops
Tom Musta
1
-0
/
+38
2015-01-07
target-ppc: Introduce tcheck
Tom Musta
1
-0
/
+17
2015-01-07
target-ppc: Introduce TM Noops
Tom Musta
1
-0
/
+38
2015-01-07
target-ppc: Introduce tbegin
Tom Musta
1
-0
/
+12
2015-01-07
target-ppc: Introduce tm_enabled Bit to CPU State
Tom Musta
1
-0
/
+8
2015-01-07
target-ppc: Eliminate set_fprf Argument From helper_compute_fprf
Tom Musta
1
-7
/
+1
2015-01-07
target-ppc: Eliminate set_fprf Argument From gen_compute_fprf
Tom Musta
1
-15
/
+23
2015-01-07
target-ppc: Fully Migrate to gen_set_cr1_from_fpscr
Tom Musta
1
-22
/
+33
2015-01-07
target-ppc: mffs. Should Set CR1 from FPSCR Bits
Tom Musta
1
-1
/
+3
2015-01-07
target-ppc: Fix Floating Point Move Instructions That Set CR1
Tom Musta
1
-20
/
+30
2015-01-07
target-ppc: Load/Store Vector Element Storage Alignment
Tom Musta
1
-8
/
+14
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