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path: root/target-ppc/translate.c
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2015-01-10Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' int...Peter Maydell1-61/+210
2015-01-07target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLYPeter Maydell1-0/+5
2015-01-07target-ppc: Introduce Privileged TM NoopsTom Musta1-0/+38
2015-01-07target-ppc: Introduce tcheckTom Musta1-0/+17
2015-01-07target-ppc: Introduce TM NoopsTom Musta1-0/+38
2015-01-07target-ppc: Introduce tbeginTom Musta1-0/+12
2015-01-07target-ppc: Introduce tm_enabled Bit to CPU StateTom Musta1-0/+8
2015-01-07target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta1-7/+1
2015-01-07target-ppc: Eliminate set_fprf Argument From gen_compute_fprfTom Musta1-15/+23
2015-01-07target-ppc: Fully Migrate to gen_set_cr1_from_fpscrTom Musta1-22/+33
2015-01-07target-ppc: mffs. Should Set CR1 from FPSCR BitsTom Musta1-1/+3
2015-01-07target-ppc: Fix Floating Point Move Instructions That Set CR1Tom Musta1-20/+30
2015-01-07target-ppc: Load/Store Vector Element Storage AlignmentTom Musta1-8/+14
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-12-23target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini1-5/+5
2014-11-20target-ppc: Altivec's mtvscr Decodes Wrong RegisterTom Musta1-1/+1
2014-11-04target-ppc: Fix Altivec Round OpcodesTom Musta1-6/+6
2014-11-04ppc: do not look at the MMU index to detect PR/HV modePaolo Bonzini1-88/+77
2014-11-04target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard1-10/+6
2014-11-04ppc: compute mask from BI using right shiftPaolo Bonzini1-3/+3
2014-11-04ppc: rename gen_set_cr6_from_fpscrPaolo Bonzini1-7/+7
2014-09-08target-ppc: Implement mulldo with TCGTom Musta1-2/+14
2014-09-08target-ppc: Clean up mullwoTom Musta1-8/+3
2014-09-08target-ppc: Clean Up mullwTom Musta1-3/+2
2014-09-08target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta1-22/+34
2014-09-08target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta1-0/+6
2014-09-08target-ppc: Special Case of rlwimi Should Use DepositTom Musta1-6/+3
2014-09-08target-ppc: Bug Fix: srawiTom Musta1-1/+1
2014-09-08target-ppc: Bug Fix: mullwTom Musta1-0/+11
2014-09-08target-ppc: Bug Fix: mullwoTom Musta1-0/+9
2014-09-08target-ppc: Bug Fix: rlwimiTom Musta1-5/+7
2014-09-08target-ppc: Bug Fix: rlwnmTom Musta1-9/+9
2014-09-08target-ppc: Bug Fix: rlwinmTom Musta1-5/+3
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-27target-ppc: Remove unused gen_qemu_ld8s()Peter Maydell1-5/+0
2014-06-27target-ppc: Remove unused IMM and d extract helpersPeter Maydell1-3/+0
2014-06-27target-ppc: fixed translation of mcrxr instructionSorav Bansal1-2/+3
2014-06-16target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy1-0/+7
2014-06-16target-ppc: Fix Temporary Variable Leak in bctarTom Musta1-1/+1
2014-06-16PPC: e500: Merge 32 and 64 bit SPE emulationAlexander Graf1-579/+132
2014-06-16PPC: SPE: Fix high-bits bitmaskAlexander Graf1-2/+2
2014-06-16target-ppc: Allow little-endian user mode.Doug Kwan1-91/+60
2014-06-16target-ppc: Fix popcntb Opcode BugTom Musta1-1/+1
2014-06-16PPC: Add dcbtls emulationAlexander Graf1-0/+12
2014-06-16PPC: Fail on leaking temporariesAlexander Graf1-0/+7
2014-06-16PPC: Fix TCG chunks that don't free their tempsAlexander Graf1-0/+7
2014-06-16target-ppc: Introduce DFP Shift SignificandTom Musta1-0/+10
2014-06-16target-ppc: Introduce DFP Insert Biased ExponentTom Musta1-0/+4
2014-06-16target-ppc: Introduce DFP Extract Biased ExponentTom Musta1-0/+4
2014-06-16target-ppc: Introduce DFP Encode BCD to DPDTom Musta1-0/+4
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