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2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-8/+6
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-15PPC: Enable hint bits for lwarx/ldarxAlexander Graf1-2/+2
The lwarx and ldarx instructions have a bit to give some hint to the CPU which is safe to ignore. We currently refuse to accept any instruction with that bit set, as it used to be declared MBZ. Let's remove the reserved bit and make the instruction work as expected. This fixes Linux boot for ppc64. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-07-13target-ppc: add vexptefp instructionAurelien Jarno1-0/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-22Fix %lld or %llx printf format useBlue Swirl1-3/+4
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-05target-ppc: Remove duplicate cpu log.Richard Henderson1-2/+0
Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25ppc: remove dead assignments, spotted by clang analyzerBlue Swirl1-1/+1
Value stored is never read. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18PPC: avoid function pointer type mismatch, spotted by clangBlue Swirl1-5/+3
Fixes clang errors: CC ppc-softmmu/translate.o /src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(read_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3748:28: note: instantiated from: if (likely(read_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(write_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3903:29: note: instantiated from: if (likely(write_cb != SPR_NOACCESS)) { Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-11target-ppc: fix evsrwu and evsrws (second try)Aurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11target-ppc: fix evsrwu and evsrwsAurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11target-ppc: fix evslw instructionAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-ppc: don't print invalid opcode messages on the consoleAurelien Jarno1-11/+0
Invalid opcode messages can be perfectly normal, for example if this code is never executed. Don't print an error message on the console, but keep the message in the log for debugging purposes. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28Revert "target-ppc: stop translation after a trap instruction"Aurelien Jarno1-12/+8
This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
2010-02-28target-ppc: stop translation after a trap instructionAurelien Jarno1-8/+12
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-27target-ppc: fix SPE evsplat* instructionsNathan Froyd1-2/+2
The shifts in the gen_evsplat* functions were expecting rA to be masked, not extracted, and so used the wrong shift amounts to sign-extend or pad with zeroes. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-9/+9
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-9/+9
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-28target-ppc: log instructions start in TCG codeAurelien Jarno1-0/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-25static and inline should came before the type of the functionsJuan Quintela1-4/+4
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-18target-ppc: optimize slw/srw/sld/srdAurelien Jarno1-49/+49
Remove a temp local variable and a jump by computing a mask with shifts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-12Fix sys-queue.h conflict for goodBlue Swirl1-2/+2
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16Replace REGX with PRIx64Blue Swirl1-1/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plxBlue Swirl1-27/+31
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16Replace always_inline with inlineBlue Swirl1-156/+162
We define inline as always_inline. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-03target-ppc: add exceptions for conditional storesNathan Froyd1-20/+51
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-08-03target-ppc: retain l{w,d}arx loaded valueNathan Froyd1-4/+9
We do this so we can check on the corresponding stc{w,d}x. whether the value has changed. It's a poor man's form of implementing atomic operations and is valid only for NPTL usermode Linux emulation. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela1-2/+2
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-13ppc tcg: fix wrong bit/mask of wrteeiBaojun Wang1-2/+2
Signed-off-by: Baojun Wang <wangbj@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12target-ppc: fix evmergelo and evmergelohiNathan Froyd1-3/+11
For 32-bit PPC targets, we translated: evmergelo rX, rX, rY as: rX-lo = rY-lo rX-hi = rX-lo which is wrong, because we should be transferring rX-lo first. This problem is fixed by swapping the order in which we write the parts of rX. Similarly, we translated: evmergelohi rX, rX, rY as: rX-lo = rY-hi rX-hi = rX-lo In this case, we can't swap the assignment statements, because that would just cause problems for: evmergelohi rX, rY, rX Instead, we detect the first case and save rX-lo in a temporary variable: tmp = rX-lo rX-lo = rY-hi rX-hi = tmp These problems don't occur on PPC64 targets because we don't split the SPE registers into hi/lo parts for such targets. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-06-20Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be usedmalc1-0/+6
uninitialized
2009-06-17Replace ELF section hack with normal tableBlue Swirl1-889/+856
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Concentrate rest of table entries to topBlue Swirl1-107/+610
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Concentrate most table entries to topBlue Swirl1-422/+291
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Clean up GEN_HANDLER2Blue Swirl1-37/+110
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Clean up GEN_HANDLERBlue Swirl1-233/+694
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-16target-ppc: expose cpu capability flagsNathan Froyd1-138/+0
Do this so other pieces of code can make decisions based on the capabilities of the CPU we're emulating. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-04-13Fix ppc-softmmu warnings on OpenBSD hostblueswir11-6/+14
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05Add new command line option -singlestep for tcg single stepping.aurel321-4/+1
This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29target-ppc: avoid nop to override next instructionaurel321-3/+3
While searching PC, always store the pc of a new instruction. Instructions that didn't generate tcg code (such as nop) prevented the next one to be referenced. Based on patch for target-alpha, r6930. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6931 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13target-ppc: use the new bswap* TCG opsaurel321-114/+15
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: rename bswap_i32/i64 functionsaurel321-11/+11
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09targe-ppc: optimize mfcr and mtcrfaurel321-3/+26
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix mfcr on ppc64-softmmuaurel321-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implement mtfsf.L encodingblueswir11-2/+6
Mtfsf can have the L bit set, so all the register contents get stored in FPSCR. Linux uses it, so let's implement it. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implment tlbielblueswir11-0/+14
Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB flush opcode only flushes an entry for the CPU it runs on, not across all CPUs in the system. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implement slbmteblueswir11-4/+19
In order to modify SLB entries on recent PPC64 machines, the slbmte instruction is used. This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB into the CPU struct later. This is required for Linux to run on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Sparse fixes: add extern to ELF opcode tables to avoid warningsblueswir11-0/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-03target-ppc: improve mfcr/mtcrfaurel321-6/+7
- use ctz32 instead of ffs - 1 - small optimisation of mtcrf - add the name of both opcodes Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02Fix mtcrf/mfcrmalc1-9/+13
Noticed by Alexander Graf git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-28Fix typo in gen_qemu_ld32sblueswir11-1/+1
When the CPU is in little endian mode, it should load values from RAM in byte swapped manner. This check is in all the ld and st functions, but misspelled in gen_qemu_ld32s. This patch fixes the misspelling and makes ppc64 Linux happier. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6654 c046a42c-6fe2-441c-8c8c-71466251a162
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