index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-ppc
/
cpu.h
Age
Commit message (
Expand
)
Author
Files
Lines
2009-02-08
Load 32 bit ELF BIOS images also on PPC64
blueswir1
1
-1
/
+2
2009-02-03
Rename spe_status to vec_status
aurel32
1
-1
/
+3
2009-02-03
Add f field to ppc_avr_t
aurel32
1
-0
/
+1
2009-01-04
Update FSF address in GPL/LGPL boilerplate
aurel32
1
-1
/
+1
2009-01-03
Add vscr access macros.
aurel32
1
-0
/
+7
2008-12-18
target-ppc: fix type of spe_acc.
aurel32
1
-1
/
+1
2008-12-15
target-ppc: add signed fields to ppc_avr_t.
aurel32
1
-0
/
+3
2008-12-11
target-ppc: remove remaining warnings
aurel32
1
-2
/
+7
2008-12-07
target-ppc: convert SPR accesses to TCG
aurel32
1
-27
/
+14
2008-12-06
target-ppc: remove dead code
aurel32
1
-5
/
+1
2008-12-06
target-ppc: convert SLB/TLB instructions to TCG
aurel32
1
-1
/
+1
2008-11-30
Common cpu_loop_exit prototype
aurel32
1
-1
/
+0
2008-11-27
target-ppc: convert POWER2 load/store instructions to TCG
aurel32
1
-3
/
+0
2008-11-27
target-ppc: convert SPE load/store to TCG
aurel32
1
-6
/
+0
2008-11-24
target-ppc: convert altivec load/store to TCG
aurel32
1
-1
/
+0
2008-11-19
target-ppc: convert fp ops to TCG
aurel32
1
-1
/
+0
2008-11-18
Refactor translation block CPU state handling (Jan Kiszka)
aliguori
1
-0
/
+8
2008-11-18
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
aliguori
1
-2
/
+6
2008-11-10
target-ppc: convert most SPE integer instructions to TCG
aurel32
1
-4
/
+8
2008-11-08
target-ppc: fix tcg fatal error on i386 host
aurel32
1
-1
/
+5
2008-11-01
target-ppc: xer access prototypes no more used & implemented
aurel32
1
-2
/
+0
2008-10-21
target-ppc: convert crf related instructions to TCG
aurel32
1
-1
/
+7
2008-10-21
target-ppc: Convert XER accesses to TCG
aurel32
1
-12
/
+11
2008-09-20
Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
blueswir1
1
-2
/
+2
2008-09-04
ppc: Convert CRF moves to TCG
aurel32
1
-1
/
+1
2008-09-04
ppc: cleanup register types
aurel32
1
-9
/
+10
2008-09-04
ppc: Convert GPR moves to TCG
aurel32
1
-11
/
+1
2008-07-01
Move interrupt_request and user_mode_only to common cpu state.
pbrook
1
-2
/
+0
2008-06-30
Move CPU save/load registration to common code.
pbrook
1
-0
/
+2
2008-06-29
Add instruction counter.
pbrook
1
-0
/
+3
2008-05-30
Fix typo.
pbrook
1
-1
/
+1
2008-05-30
Move clone() register setup to target specific code. Handle fork-like clone.
pbrook
1
-0
/
+11
2008-05-29
Push common interrupt variables to cpu-defs.h (Glauber Costa)
bellard
1
-2
/
+0
2008-05-28
moved halted field to CPU_COMMON
bellard
1
-2
/
+0
2008-05-06
PPC: fix definition of msr_spe
aurel32
1
-1
/
+1
2007-12-10
Cleanup: remove useless TARGET_GPR_BITS definition.
j_mayer
1
-3
/
+0
2007-12-10
Fix PowerPC 74xx definitions.
j_mayer
1
-2
/
+3
2007-11-24
Fix incorrect debug prints (reported by Paul Brook).
j_mayer
1
-3
/
+19
2007-11-23
Revert foolish patch.
j_mayer
1
-4
/
+3
2007-11-23
Fix ppc32 register dumps on 64-bit hosts.
pbrook
1
-3
/
+4
2007-11-21
Fix PowerPC 7xx definitions.
j_mayer
1
-1
/
+18
2007-11-19
Remove shared macro used to define PowerPC implementations instructions sets:
j_mayer
1
-2
/
+9
2007-11-19
PowerPC 620 MMU do not have the same exact behavior as standard
j_mayer
1
-12
/
+15
2007-11-19
New PowerPC CPU flag to define the decrementer and time-base source clock.
j_mayer
1
-12
/
+16
2007-11-17
Improve PowerPC instructions set dump.
j_mayer
1
-1
/
+0
2007-11-17
Add definitions for Freescale PowerPC implementations,
j_mayer
1
-387
/
+440
2007-11-17
Define Freescale cores specific MMU model, exceptions and input bus.
j_mayer
1
-12
/
+38
2007-11-17
PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.
j_mayer
1
-3
/
+21
2007-11-17
Make the PowerPC MMU model, exception model and input bus model
j_mayer
1
-7
/
+9
2007-11-17
Add missing definition for number of input pins for the PowerPC 970 bus.
j_mayer
1
-0
/
+1
[next]