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path: root/target-ppc/cpu-models.c
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2014-07-08target-ppc: Remove POWER7+ and POWER8E familiesAlexey Kardashevskiy1-2/+2
POWER8E is architecturally equal to POWER8 and POWER7+ is equal to POWER7. Also no user space tool makes any difference for CPU node name in the device tree (such as PowerPC,POWER7@0 vs. PowerPC,POWER7+@0). So there is no point in emulating POWER7+ and POWER8E apart from POWER7 and POWER8. Also, the previos patch implemented multiple PVR mask support per CPU class so POWER7 class now covers both POWER7 and POWER7+ CPUs, same is valid for POWER8/8E. This removes POWER7+ and POWER8E classes. This replaces references to POWER7P/POWER8E families with POWER7/POWER8 families. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-07-08target-ppc: Add pvr_match() callbackAlexey Kardashevskiy1-1/+0
So far it was enough to have a base PVR value and mask per CPU family such as POWER7 or POWER8. However there CPUs which are completely architecturally compatible but have different PVRs such as POWER7/POWER7+ and POWER8/POWER8E. For these CPUs, top 16 bits are CPU family and low 16 bits are the version. The families have PVR base values different enough so defining a mask which would cover both (or potentially more) CPUs within the family is not possible. This adds a pvr_match() callback to PowerPCCPUClass. The default handler simply compares PVR defined in the class. This implements ppc_pvr_match_power7/ppc_pvr_match_power8 callbacks for POWER7/8 families. These check for POWER7/POWER7+ and POWER8/POWER8E. This changes ppc_cpu_compare_class_pvr_mask() not to check masks but use the pvr_match() callback. Since all server CPUs use the same mask, this defines one mask value - CPU_POWERPC_POWER_SERVER_MASK - which is used everywhere now. This removes other mask definitions. This removes pvr_mask from PowerPCCPUClass as it is not used anymore. This removes pvr initialization for POWER7/8 families as it is not used to find the class, the pvr_match() callback is used instead. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-27target-ppc: Add support for POWER8 pvr 0x4D0000Alexey Kardashevskiy1-0/+3
At the moment QEMU knows about one version of POWER8 CPU with PVR 0x4B.0000. This CPU class is defined as "POWER8". The linux kernel names it as "POWER8E" which is different from the name QEMU uses. Now we get another version of POWER8 which is architecturally equivalent to POWER8E but has different PVR 0x4D.0000 so QEMU fails to find a PPC CPU class on these machines. The linux kernel names these CPUs as "POWER8". This renames the existing "POWER8" to "POWER8E" to be more precise and stay in sync with the linux kernel. This adds a new "POWER8" family which calls POWER8E class init function and defines own PVR mask (used to match a CPU class) and desc (used to create dynamic version-less CPU class). This does not change CPU class fw_name attribute as the host POWER8 firmware keeps using "PowerPC,POWER8" on both POWER8 and POWER8E. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Merge 970FX and 970MP into a single 970 classAlexey Kardashevskiy1-7/+7
The differences between classes were: 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all; 2. check_pow() callback, HID0 format is the same so should be the same 0x01C00000 which means "deep nap", "doze" and "nap" bits set; 3. LPCR - 970 does not have it but 970MP had one (by mistake). This fixes wrong differences and makes one 970 class. This fixes wrong registration of LPCR which is not present on 970. This defines HID0 bits and uses them in check_pow_970(). This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to 970 class as we do not emulate hypervisor in QEMU anyway. This does not remove check_pow_970FX now as it is still used by POWER5+ class, this will be addressed later. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Make all e500 CPUs SVR awareAlexander Graf1-14/+14
Our pre-e500mc e500 CPU types didn't get instanciated with SVR information, even though those systems do support the SVR register. Spawn them with the SVR tag so that they don't get confused when someone tries to read SPR_SVR. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Remove redundant POWER7 declarationsAlexey Kardashevskiy1-4/+0
At the moment there are 3 versions of POWER7 CPUs defined. However we do not emulate these CPUs diffent and it does not make much sense to keep them all. This removes POWER7_v2.0 and POWER7_v2.1 and leaves just one versioned CPU per family which is POWER7_v2.3 with POWER7 alias. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove powerpc 970gxAlexey Kardashevskiy1-2/+0
The 970GX definition was added in 2007 and it made sense then but this version has never been released to the markets and it does not exist in the real world so there is no point in emulating it. This removes 970GX. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: move POWER7+ to a separate familyAlexey Kardashevskiy1-1/+1
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy1-0/+1
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and a CPU version in lower 16 bits. Since there is no significant change in behavior between versions, there is no point to add every single CPU version in QEMU's CPU list. Also, new CPU versions of already supported CPU won't break the existing code. This adds PVR value/mask support for KVM, i.e. for -cpu host option. As CPU family class name for POWER7 is "POWER7-family", there is no need to touch aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-08-07target-ppc: Add POWER5+ v2.1 CPU modelAndreas Färber1-0/+2
Let's avoid -cpu host barfing at this PVR. Linux recognizes it as "POWER5+ (gs) v2.1". Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-5-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Prepare POWER5P CPU familyAndreas Färber1-2/+0
It is ISA 2.03. Modelled as 970FX minus AltiVec flag. Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-4-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Turn POWER5gr CPU into alias for POWER5Andreas Färber1-2/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-3-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Turn POWER5gs CPU into alias for POWER5+Andreas Färber1-2/+1
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375321323-29954-2-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-07target-ppc: Fix POWER7+ modelAndreas Färber1-2/+3
Commit 03a15a5436ed7723f406f15cc3798aa9991e75b5 claimed to add a POWER7+ model but instead added a "POWER7P" model, with an unhelpful "POWER7P" description on top. Fix this to "POWER7+" as we already have "POWER3+", "POWER4+" and "POWER5+" and there being no reason to deviate with the user-visible command line -cpu POWER7P from the marketing name POWER7+. Further, don't needlessly deviate from the scheme of naming PVR constant, QOM type and device description after the exact revision that is in fact encoded in the PVR used. That way, we can change the user-friendly alias -cpu POWER7+ to point to a different revision if we so desire, while not polluting the type namespace. This naming scheme is sensible and completely orthogonal to how PVRs may or may not get matched to CPU types. Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375736387-8429-1-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-05target-ppc: Add POWER7+ CPU modelAlexey Kardashevskiy1-0/+2
This patch adds CPU PVR definition for POWER7+. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1375412374-24701-1-git-send-email-aik@ozlabs.ru Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-11target-ppc: Add POWER8 v1.0 CPU modelPrerna Saxena1-0/+3
This patch adds CPU PVR definition for POWER8, and enables QEMU to launch guests on POWER8 hardware. Signed-off-by: Prerna Saxena <prerna@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Paul Mackerras <paulus@samba.org> Reviewed-by: Andreas Farber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11e600 core for MPC86xx processorsJulio Guerra1-6/+4
MPC86xx processors are based on the e600 core, which is not the case in qemu where it is based on the 7400 processor. This patch creates the e600 core and instantiates the MPC86xx processors based on it. Therefore, adding the high BATs, the SPRG 4..7 registers, which are e600-specific [1], and a HW MMU model (as 7400). This allows to define the MPC8610 processor too. Tested with a kernel using the HW TLB misses. [1] http://cache.freescale.com/files/32bit/doc/ref_manual/E600CORERM.pdf Signed-off-by: Julio Guerra <guerr@julio.in> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01PPC: Introduce an alias cache for faster lookupsAlexander Graf1-1/+1
When running QEMU with "-cpu ?" we walk through every alias for every target CPU we know about. This takes several seconds on my very fast host system. Let's introduce a class object cache in the alias table. Using that we don't have to go through the tedious work of finding our target class. Instead, we can just go directly from the alias name to the target class pointer. This patch brings -cpu "?" to reasonable times again. Before: real 0m4.716s After: real 0m0.025s Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson1-1/+1
The PowerPC 620 was the very first 64-bit PowerPC implementation, but hardly anyone ever actually used the chips. qemu notionally supports the 620, but since we don't actually have code to implement the segment table, the support is broken (quite likely in other ways too). This patch, therefore, removes all remaining pieces of 620 support, to stop it cluttering up the platforms we actually care about. This includes removing support for the ASR register, used only on segment table based machines. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Move CPU aliases out of translate_init.cAndreas Färber1-0/+194
Move array of CPU aliases to cpu-models.c, alongside model definitions. This requires to zero-terminate the aliases array since ARRAY_SIZE() can no longer be used in translate_init.c then. Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix remaining microcontroller typos among modelsAndreas Färber1-6/+6
controler -> controller Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Split model definitions out of translate_init.cAndreas Färber1-0/+1225
Now that model definitions only reference their parent type, model definitions are independent of the family definitions and can be compiled independently of TCG translation. Keep all #if defined(TODO) code local to cpu-models.c. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
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