aboutsummaryrefslogtreecommitdiff
path: root/target-openrisc
AgeCommit message (Expand)AuthorFilesLines
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-24target-openrisc: remove conflicting definitions from cpu.hAurelien Jarno1-18/+0
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-5/+5
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity2-12/+12
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-07-27target-or32: Add linux user supportJia Liu1-0/+12
2012-07-27target-or32: Add system instructionsJia Liu5-1/+321
2012-07-27target-or32: Add timer supportJia Liu1-0/+22
2012-07-27target-or32: Add PIC supportJia Liu1-0/+3
2012-07-27target-or32: Add instruction translationJia Liu1-0/+1734
2012-07-27target-or32: Add float instruction helpersJia Liu3-1/+335
2012-07-27target-or32: Add int instruction helpersJia Liu3-1/+85
2012-07-27target-or32: Add exception supportJia Liu5-2/+89
2012-07-27target-or32: Add interrupt supportJia Liu5-2/+134
2012-07-27target-or32: Add MMU supportJia Liu3-2/+303
2012-07-27target-or32: Add target stubs and QOM cpuJia Liu8-0/+792