riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2012-12-16	exec: refactor cpu_restore_state	Blue Swirl	1	-9/+1
2012-12-08	TCG: Use gen_opc_instr_start from context instead of global variable.	Evgeny Voevodin	1	-3/+3
2012-12-08	TCG: Use gen_opc_icount from context instead of global variable.	Evgeny Voevodin	1	-1/+1
2012-12-08	TCG: Use gen_opc_pc from context instead of global variable.	Evgeny Voevodin	1	-2/+2
2012-11-24	target-openrisc: remove conflicting definitions from cpu.h	Aurelien Jarno	1	-18/+0
2012-11-17	TCG: Use gen_opc_buf from context instead of global variable.	Evgeny Voevodin	1	-4/+5
2012-11-17	TCG: Use gen_opc_ptr from context instead of global variable.	Evgeny Voevodin	1	-5/+5
2012-11-10	disas: avoid using cpu_single_env	Blue Swirl	1	-1/+1
2012-10-31	cpus: Pass CPUState to [qemu_]cpu_has_work()	Andreas Färber	1	-1/+3
2012-10-23	Rename target_phys_addr_t to hwaddr	Avi Kivity	2	-12/+12
2012-09-27	Emit debug_insn for CPU_LOG_TB_OP_OPT as well.	Richard Henderson	1	-1/+1
2012-07-27	target-or32: Add linux user support	Jia Liu	1	-0/+12
2012-07-27	target-or32: Add system instructions	Jia Liu	5	-1/+321
2012-07-27	target-or32: Add timer support	Jia Liu	1	-0/+22
2012-07-27	target-or32: Add PIC support	Jia Liu	1	-0/+3
2012-07-27	target-or32: Add instruction translation	Jia Liu	1	-0/+1734
2012-07-27	target-or32: Add float instruction helpers	Jia Liu	3	-1/+335
2012-07-27	target-or32: Add int instruction helpers	Jia Liu	3	-1/+85
2012-07-27	target-or32: Add exception support	Jia Liu	5	-2/+89
2012-07-27	target-or32: Add interrupt support	Jia Liu	5	-2/+134
2012-07-27	target-or32: Add MMU support	Jia Liu	3	-2/+303
2012-07-27	target-or32: Add target stubs and QOM cpu	Jia Liu	8	-0/+792