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2013-02-01target-openrisc: Rename CPU subtypesAndreas Färber1-4/+11
2013-02-01target-openrisc: TYPE_OPENRISC_CPU should be abstractAndreas Färber1-1/+1
2013-01-28target-openrisc: Use type_register() instead of type_register_static()Andreas Färber1-1/+1
2013-01-28target-openrisc: Catch attempt to instantiate abstract type in cpu_init()Andreas Färber1-1/+2
2013-01-27target-openrisc: Detect attempt to instantiate non-CPU type in cpu_init()Andreas Färber1-2/+22
2013-01-27target-openrisc: Clean up triple QOM castsAndreas Färber6-24/+24
2013-01-27target-openrisc: Drop OpenRISCCPUListAndreas Färber1-7/+2
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber1-1/+1
2012-12-19fpu: move public header file to include/fpuPaolo Bonzini1-1/+1
2012-12-19misc: move include files to include/qemu/Paolo Bonzini4-5/+5
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini6-14/+14
2012-12-19qapi: move include files to include/qobject/Paolo Bonzini1-1/+1
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-9/+1
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-24target-openrisc: remove conflicting definitions from cpu.hAurelien Jarno1-18/+0
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-5/+5
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-1/+3
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity2-12/+12
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-07-27target-or32: Add linux user supportJia Liu1-0/+12
2012-07-27target-or32: Add system instructionsJia Liu5-1/+321
2012-07-27target-or32: Add timer supportJia Liu1-0/+22
2012-07-27target-or32: Add PIC supportJia Liu1-0/+3
2012-07-27target-or32: Add instruction translationJia Liu1-0/+1734
2012-07-27target-or32: Add float instruction helpersJia Liu3-1/+335
2012-07-27target-or32: Add int instruction helpersJia Liu3-1/+85
2012-07-27target-or32: Add exception supportJia Liu5-2/+89
2012-07-27target-or32: Add interrupt supportJia Liu5-2/+134
2012-07-27target-or32: Add MMU supportJia Liu3-2/+303
2012-07-27target-or32: Add target stubs and QOM cpuJia Liu8-0/+792
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