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path: root/target-openrisc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2016-01-29openrisc: Clean up includesPeter Maydell1-1/+1
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson1-0/+5
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson1-38/+4
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson1-2/+2
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson1-0/+3
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson1-17/+7
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson1-2/+2
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson1-4/+1
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson1-1/+1
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-1/+1
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson1-11/+11
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite1-1/+1
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson1-18/+16
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-8/+5
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-01-15target-openrisc: bugfix for dec_sys to decode instructions correctlyDavid Morrison1-1/+1
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova1-0/+3
2014-06-29openrisc: fix commentMichael S. Tsirkin1-2/+2
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-0/+1
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-3/+2
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
2014-02-12target-openrisc: Use new qemu_ld/st opcodesRichard Henderson1-67/+32
2013-12-23openrisc: Fix spelling in comment (transaltion -> translation)Stefan Weil1-1/+1
2013-11-20target-openrisc: Remove unnecessary code generated by jump instructionsSebastian Macke1-19/+26
2013-11-20target-openrisc: Speed up move instructionSebastian Macke1-23/+27
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-2/+0
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber1-1/+1
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-5/+7
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-23qemu-log: Remove qemu_log_try_set_file() and its usersPeter Maydell1-2/+0
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-2/+2
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-5/+5
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+1
2012-07-27target-or32: Add system instructionsJia Liu1-0/+26
2012-07-27target-or32: Add instruction translationJia Liu1-0/+1734
2012-07-27target-or32: Add target stubs and QOM cpuJia Liu1-0/+75
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