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2012-10-31target-mips: Change TODO fileJia Liu1-2/+1
2012-10-31target-mips: Add ASE DSP processorsJia Liu1-0/+52
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu3-0/+995
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu3-0/+635
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu3-0/+311
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu3-0/+1499
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu3-0/+618
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu3-3/+1812
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu1-0/+88
2012-10-31target-mips: Add ASE DSP branch instructionsJia Liu1-0/+36
2012-10-31Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu1-27/+95
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu3-2/+47
2012-10-31target-mips: Add ASE DSP internal functionsJia Liu2-1/+1064
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber1-5/+6
2012-10-28target-mips: Use TCG registers for the FPU.Richard Henderson1-42/+54
2012-10-28target-mips: rename helper flagsAurelien Jarno1-53/+53
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity3-18/+18
2012-10-17target-mips: Pass MIPSCPU to mips_vpe_sleep()Andreas Färber1-3/+7
2012-10-17target-mips: Pass MIPSCPU to mips_tc_sleep()Andreas Färber1-3/+5
2012-10-17target-mips: Pass MIPSCPU to mips_vpe_is_wfi()Andreas Färber1-4/+8
2012-10-17target-mips: Pass MIPSCPU to mips_tc_wake()Andreas Färber1-3/+8
2012-10-17target-mips: Clean up other_cpu in helper_{d,e}vpe()Andreas Färber1-14/+14
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
2012-09-19target-mips: Implement Loongson Multimedia InstructionsRichard Henderson4-4/+1180
2012-09-19target-mips: Always evaluate debugging macro argumentsRichard Henderson1-14/+17
2012-09-19target-mips: Fix MIPS_DEBUG.Richard Henderson1-36/+38
2012-09-19target-mips: Set opn in gen_ldst_multiple.Richard Henderson1-0/+6
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl5-1085/+1162
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki3-62/+52
2012-08-27target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson1-1/+9
2012-08-27target-mips: add privilege level check to several Cop0 instructionsEric Johnson1-0/+9
2012-08-27mips-linux-user: Always support rdhwr.Richard Henderson1-0/+4
2012-08-27target-mips: Streamline indexed cp1 memory addressing.Richard Henderson1-2/+1
2012-08-27Fix order of CVT.PS.S operandsRichard Sandiford1-1/+1
2012-08-27Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford1-2/+2
2012-08-24target-mips: Fix some helper functions (VR54xx multiplication)Stefan Weil1-46/+29
2012-08-23target-mips: Enable access to required RDHWR hardware registersMeador Inge1-2/+3
2012-08-09MIPS: Correct FCR0 initializationNathan Froyd1-0/+1
2012-06-07build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini1-1/+2
2012-06-07build: move libobj-y variable to nested Makefile.objsPaolo Bonzini1-1/+3
2012-06-07build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini1-0/+1
2012-06-04Kill off cpu_state_reset()Andreas Färber1-0/+3
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2-4/+12
2012-06-04target-mips: Use cpu_reset() in do_interrupt()Andreas Färber1-1/+2
2012-06-04target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber1-1/+1
2012-05-19mips: Fix BC1ANY[24]F instructionsRichard Sandiford1-4/+4
2012-05-12target-mips: Remove commented-out function declarationAndreas Färber1-1/+0
2012-05-03target-mips: Remove unused inline functionStefan Weil1-6/+0
2012-05-01Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpuBlue Swirl4-2/+148
2012-04-30target-mips: Start QOM'ifying CPU initAndreas Färber2-1/+9
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