| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2008-04-11 | Remove osdep.c/qemu-img code duplication | aurel32 | 1 | -0/+1 |
| 2008-03-29 | Fix infinite loop when invalidating TLB, by Herve Poussineau. | ths | 1 | -1/+1 |
| 2008-02-12 | Make MIPS MT implementation more cache friendly. | ths | 5 | -59/+59 |
| 2008-02-01 | use the TCG code generator | bellard | 2 | -55/+6 |
| 2008-01-09 | Fix typo which broke MIPS32R2 64-bit FPU support. | ths | 1 | -1/+1 |
| 2008-01-08 | Fix broken absoluteness check for cabs.d.*. | ths | 1 | -2/+2 |
| 2008-01-04 | Handle some more exception types. | ths | 1 | -29/+43 |
| 2008-01-03 | Fix exception debug output. | ths | 1 | -39/+36 |
| 2007-12-30 | MIPS COP1X (and related) instructions, by Richard Sandiford. | ths | 3 | -18/+74 |
| 2007-12-28 | Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford. | ths | 1 | -3/+3 |
| 2007-12-26 | De-cruft exception definitions, and implement nicer debug output. | ths | 2 | -26/+65 |
| 2007-12-25 | Support for VR5432, and some of its special instructions. Original patch | ths | 6 | -7/+405 |
| 2007-12-25 | 5K and 20K are Release 1 CPUs. | ths | 1 | -3/+3 |
| 2007-12-25 | Avoid host FPE for overflowing division on MIPS, by Richard Sandiford. | ths | 1 | -3/+10 |
| 2007-12-25 | Improved PABITS handling, and config register fixes. | ths | 4 | -56/+106 |
| 2007-12-24 | Update debug code to match new accumulator register layout. | ths | 1 | -4/+4 |
| 2007-12-24 | Fix CCRes value for 20Kc. | ths | 1 | -1/+1 |
| 2007-12-17 | MIPS TODO: mention unimplemented system controllers. | ths | 1 | -0/+2 |
| 2007-12-17 | Update MIPS TODO. The mipsnet failure is caused by a kernel bug. | ths | 1 | -6/+0 |
| 2007-12-09 | Handle cpu_model in copy_cpu(), by Kirill A. Shutemov. | ths | 1 | -0/+1 |
| 2007-12-02 | Larger physical address space for 32-bit MIPS. | ths | 1 | -0/+3 |
| 2007-11-26 | Micro-optimize back-to-back store-load sequences. | ths | 1 | -103/+135 |
| 2007-11-22 | Optimize the conventional move operation. | ths | 1 | -0/+6 |
| 2007-11-22 | Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno. | ths | 1 | -4/+4 |
| 2007-11-19 | Add older 4Km variants. | ths | 1 | -0/+34 |
| 2007-11-18 | Add strict checking mode for softfp code. | pbrook | 1 | -4/+4 |
| 2007-11-18 | Fix MIPS64 R2 instructions. | ths | 3 | -30/+34 |
| 2007-11-18 | Use a valid PRid. | ths | 1 | -1/+1 |
| 2007-11-17 | Fix int/float inconsistencies. | pbrook | 3 | -36/+34 |
| 2007-11-14 | Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP | ths | 1 | -2/+19 |
| 2007-11-10 | added cpu_model parameter to cpu_init() | bellard | 3 | -29/+23 |
| 2007-11-09 | Use FORCE_RET, scrap RETURN which was implemented in target-specific code. | ths | 5 | -424/+418 |
| 2007-11-09 | Move kernel loader parameters from the cpu state to being board specific. | ths | 1 | -5/+0 |
| 2007-11-08 | Clean out the N32 macros from target-mips, and introduce MIPS ABI specific | ths | 9 | -61/+61 |
| 2007-11-08 | Formatting fix. | ths | 1 | -1/+1 |
| 2007-10-29 | Adjust s390 addresses (the MSB is defined as "to be ignored"). | ths | 1 | -1/+5 |
| 2007-10-29 | Preliminary MIPS64R2 mode. | ths | 1 | -0/+21 |
| 2007-10-29 | Fix logic bug which broke TLBL/TLBS handling somewhat. | ths | 1 | -3/+3 |
| 2007-10-29 | Restrict CP0_PerfCnt to legal values. | ths | 1 | -1/+1 |
| 2007-10-28 | Implement missing MIPS supervisor mode bits. | ths | 6 | -35/+49 |
| 2007-10-27 | Add sharable clz/clo inline functions and use them for the mips target. | ths | 3 | -49/+33 |
| 2007-10-26 | The other half of the mul64 rework. Sorry for the breakage, I committed | ths | 1 | -2/+2 |
| 2007-10-24 | Remove bogus instruction decode. | ths | 1 | -1/+0 |
| 2007-10-24 | Force proper sign extension for mfc0/mfhc0 on MIPS64. | ths | 1 | -2/+2 |
| 2007-10-23 | Fix writable length of the index register. | ths | 1 | -1/+8 |
| 2007-10-23 | Enforce proper sign extension for lwl/lwr on MIPS64. | ths | 1 | -1/+3 |
| 2007-10-23 | Fix CLO calculation for MIPS64. And a small code cleanup. | ths | 1 | -5/+5 |
| 2007-10-23 | Use the standard ASE check for MIPS-3D and MT. | ths | 3 | -93/+80 |
| 2007-10-23 | Switch bc1any* instructions off if no MIPS-3D is implemented. | ths | 1 | -1/+9 |
| 2007-10-20 | Handle IBE on MIPS properly. | ths | 2 | -0/+11 |
