| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-10-14 | target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX | Peter Maydell | 1 | -19/+1 |
| 2014-10-14 | target-mips/dsp_helper.c: Add ifdef guards around various functions | Peter Maydell | 1 | -1/+16 |
| 2014-10-14 | target-mips/translate.c: Add ifdef guard around check_mips64() | Peter Maydell | 1 | -0/+2 |
| 2014-10-14 | target-mips/op_helper.c: Remove unused do_lbu() function | Peter Maydell | 1 | -1/+0 |
| 2014-10-14 | target-mips/dsp_helper.c: Remove unused function get_DSPControl_24() | Peter Maydell | 1 | -9/+0 |
| 2014-10-14 | target-mips: fix broken MIPS16 and microMIPS | Yongbok Kim | 2 | -188/+123 |
| 2014-10-14 | target-mips/translate.c: Update OPC_SYNCI | Dongxue Zhang | 1 | -1/+6 |
| 2014-10-14 | target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA | Leon Alrae | 1 | -0/+30 |
| 2014-10-14 | target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions | Yongbok Kim | 1 | -2/+16 |
| 2014-10-14 | target-mips: do not allow Status.FR=0 mode in 64-bit FPU | Leon Alrae | 1 | -0/+6 |
| 2014-10-14 | target-mips: add new Floating Point Comparison instructions | Yongbok Kim | 3 | -2/+342 |
| 2014-10-14 | target-mips: add new Floating Point instructions | Leon Alrae | 3 | -44/+521 |
| 2014-10-14 | target-mips: add AUI, LSA and PCREL instruction families | Leon Alrae | 1 | -14/+189 |
| 2014-10-13 | target-mips: add compact and CP1 branches | Yongbok Kim | 1 | -14/+459 |
| 2014-10-13 | target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions | Yongbok Kim | 3 | -12/+136 |
| 2014-10-13 | target-mips: Status.UX/SX/KX enable 32-bit address wrapping | Leon Alrae | 2 | -9/+15 |
| 2014-10-13 | target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 | Leon Alrae | 1 | -59/+62 |
| 2014-10-13 | target-mips: redefine Integer Multiply and Divide instructions | Leon Alrae | 1 | -21/+322 |
| 2014-10-13 | target-mips: move PREF, CACHE, LLD and SCD instructions | Leon Alrae | 1 | -1/+28 |
| 2014-10-13 | target-mips: signal RI Exception on DSP and Loongson instructions | Leon Alrae | 1 | -97/+98 |
| 2014-10-13 | target-mips: split decode_opc_special* into *_r6 and *_legacy | Leon Alrae | 1 | -68/+160 |
| 2014-10-13 | target-mips: extract decode_opc_special* from decode_opc | Leon Alrae | 1 | -805/+845 |
| 2014-10-13 | target-mips: move LL and SC instructions | Leon Alrae | 1 | -2/+26 |
| 2014-10-13 | target-mips: add SELEQZ and SELNEZ instructions | Leon Alrae | 1 | -2/+16 |
| 2014-10-13 | target-mips: signal RI Exception on instructions removed in R6 | Leon Alrae | 1 | -8/+56 |
| 2014-10-13 | target-mips: define ISA_MIPS64R6 | Leon Alrae | 1 | -9/+19 |
| 2014-10-06 | gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag | Peter Maydell | 1 | -0/+1 |
| 2014-09-25 | target-mips: Use cpu_exec_interrupt qom hook | Richard Henderson | 3 | -0/+19 |
| 2014-08-12 | trace: [tcg] Include TCG-tracing header on all targets | Lluís Vilanova | 1 | -0/+3 |
| 2014-08-07 | target-mips: Ignore unassigned accesses with KVM | James Hogan | 1 | -0/+11 |
| 2014-07-28 | target-mips/translate.c: Free TCG in OPC_DINSV | Dongxue Zhang | 1 | -0/+3 |
| 2014-07-09 | mips/kvm: Disable FPU on reset with KVM | James Hogan | 1 | -0/+7 |
| 2014-07-05 | mips/kvm: Init EBase to correct KSEG0 | James Hogan | 1 | -1/+7 |
| 2014-06-20 | target-mips: copy CP0_Config1 into DisasContext | Aurelien Jarno | 1 | -9/+11 |
| 2014-06-20 | Merge remote-tracking branch 'remotes/kvm/uq/master' into staging | Peter Maydell | 6 | -13/+758 |
| 2014-06-18 | target-mips: implement UserLocal Register | Petar Jovanovic | 4 | -13/+83 |
| 2014-06-18 | target-mips: Enable KVM support in build system | Sanjay Lal | 1 | -0/+1 |
| 2014-06-18 | target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset() | James Hogan | 1 | -0/+8 |
| 2014-06-18 | target-mips: kvm: Add main KVM support for MIPS | Sanjay Lal | 2 | -0/+709 |
| 2014-06-18 | target-mips: get_physical_address: Add KVM awareness | James Hogan | 1 | -7/+26 |
| 2014-06-18 | target-mips: get_physical_address: Add defines for segment bases | James Hogan | 1 | -6/+12 |
| 2014-06-18 | target-mips: Reset CPU timer consistently | James Hogan | 1 | -0/+2 |
| 2014-06-05 | softmmu: introduce cpu_ldst.h | Paolo Bonzini | 2 | -5/+2 |
| 2014-06-05 | softmmu: commonize helper definitions | Paolo Bonzini | 1 | -14/+0 |
| 2014-06-05 | softmmu: move ALIGNED_ONLY to cpu.h | Paolo Bonzini | 2 | -1/+1 |
| 2014-06-05 | softmmu: make do_unaligned_access a method of CPU | Paolo Bonzini | 3 | -6/+8 |
| 2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson | 5 | -12/+5 |
| 2014-03-27 | target-mips: Avoid shifting left into sign bit | Peter Maydell | 4 | -17/+17 |
| 2014-03-25 | target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode | Petar Jovanovic | 1 | -35/+44 |
| 2014-03-13 | cputlb: Change tlb_set_page() argument to CPUState | Andreas Färber | 1 | -1/+1 |
