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target-mips
Age
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Author
Files
Lines
2010-07-03
move cpu_pc_from_tb to target-*/exec.h
Paolo Bonzini
2
-7
/
+7
2010-07-03
remove unused stuff from */exec.h
Paolo Bonzini
2
-9
/
+6
2010-07-01
target-mips: add Loongson support prefetch
Aurelien Jarno
1
-35
/
+43
2010-07-01
target-mips: split load and store
Aurelien Jarno
1
-155
/
+183
2010-06-30
target-mips: fix DINSU instruction
Aurelien Jarno
1
-1
/
+1
2010-06-29
target-mips: enable movn/movz on loongson 2E & 2F
Aurelien Jarno
1
-1
/
+2
2010-06-29
MIPS: Initial support of fulong mini pc (CPU definition)
Huacai Chen
2
-0
/
+39
2010-06-09
target-mips: Fix compilation
Stefan Weil
1
-1
/
+1
2010-06-09
target-mips: add microMIPS exception handler support
Nathan Froyd
2
-6
/
+16
2010-06-09
target-mips: microMIPS ASE support
Nathan Froyd
4
-5
/
+2531
2010-06-09
target-mips: mips16 cleanups
Nathan Froyd
1
-7
/
+17
2010-06-09
target-mips: refactor c{, abs}.cond.fmt insns
Nathan Froyd
1
-83
/
+81
2010-06-09
target-mips: move FP FMT comments closer to the definitions
Aurelien Jarno
1
-14
/
+14
2010-06-09
target-mips: define constants for magic numbers
Nathan Froyd
1
-142
/
+295
2010-06-08
target-mips: break out [ls][wd]c1 and rdhwr insn generation
Nathan Froyd
1
-47
/
+59
2010-05-05
target-mips: Remove duplicate CPU log.
Richard Henderson
1
-6
/
+0
2010-04-09
target-mips: Fix format specifiers for fpu_fprintf
Stefan Weil
1
-14
/
+20
2010-04-08
target-mips: Fix one more format specifier for cpu_fprintf
Stefan Weil
1
-1
/
+3
2010-04-08
remove TARGET_* defines from translate-all.c
Paolo Bonzini
1
-0
/
+2
2010-03-17
Large page TLB flush
Paul Brook
1
-3
/
+4
2010-03-13
target-mips: update address space definitions
Aurelien Jarno
1
-4
/
+4
2010-03-12
Target specific usermode cleanup
Paul Brook
2
-2
/
+14
2010-03-12
Remove cpu_get_phys_page_debug from userspace emulation
Paul Brook
1
-4
/
+2
2010-03-12
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Richard Henderson
1
-0
/
+4
2010-03-04
target-mips: use newer logical ops
Aurelien Jarno
1
-8
/
+4
2010-03-02
target-mips: use setcond when possible
Aurelien Jarno
1
-77
/
+20
2010-02-23
target-mips: fix ROTR and DROTR by zero
Nathan Froyd
1
-0
/
+4
2010-02-23
target-mips: fix CpU exception for coprocessor 0
Nathan Froyd
1
-1
/
+1
2010-02-23
target-mips: remove useless sign extension
Aurelien Jarno
1
-2
/
+0
2010-02-06
target-mips: don't call cpu_loop_exit() from helper.c
Aurelien Jarno
3
-8
/
+22
2010-01-19
kill regs_to_env and env_to_regs
Paolo Bonzini
1
-8
/
+0
2009-12-17
target-mips: No MIPS16 support for 4Kc, 4KEc cores
Stefan Weil
1
-3
/
+3
2009-12-16
target-mips: 4Kc, 4KEc cores do not support MIPS16
Stefan Weil
1
-3
/
+3
2009-12-13
target-mips: fix user-mode emulation startup
Nathan Froyd
2
-8
/
+8
2009-12-13
target-mips: set Config1.CA for MIPS16-aware CPUs
Nathan Froyd
1
-9
/
+18
2009-12-13
target-mips: add copyright notice for mips16 work
Nathan Froyd
2
-1
/
+1
2009-12-13
target-mips: add mips16 instruction decoding
Nathan Froyd
1
-9
/
+1063
2009-12-13
target-mips: add enums for MIPS16 opcodes
Nathan Froyd
1
-0
/
+112
2009-12-13
target-mips: split out delay slot handling
Nathan Froyd
1
-55
/
+79
2009-12-13
target-mips: add gen_base_offset_addr
Nathan Froyd
1
-24
/
+16
2009-12-13
target-mips: make gen_compute_branch 16/32-bit-aware
Nathan Froyd
1
-7
/
+8
2009-12-13
target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
Nathan Froyd
1
-139
/
+148
2009-12-13
target-mips: change interrupt bits to be mips16-aware
Nathan Froyd
2
-24
/
+44
2009-12-13
target-mips: add new HFLAGs for JALX and 16/32-bit delay slots
Nathan Froyd
1
-19
/
+28
2009-11-30
target-mips: use physical address in lladdr
Aurelien Jarno
3
-28
/
+61
2009-11-30
target-mips: add a function to do virtual -> physical translations
Aurelien Jarno
2
-0
/
+25
2009-11-30
target-mips: split code raising MMU exception in a separate function
Aurelien Jarno
1
-46
/
+53
2009-11-30
target-mips: factorize load/store code in op_helper.c
Aurelien Jarno
1
-152
/
+100
2009-11-22
target-mips: fix physical address type in MMU functions
Aurelien Jarno
2
-11
/
+11
2009-11-22
target-mips: make CP0_LLAddr register CPU dependent
Aurelien Jarno
5
-4
/
+49
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