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2009-12-17target-mips: No MIPS16 support for 4Kc, 4KEc coresStefan Weil1-3/+3
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487. 4Kc and 4KEc don't support MIPS16. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-16target-mips: 4Kc, 4KEc cores do not support MIPS16Stefan Weil1-3/+3
4Kc, 4KEc cores do not support MIPS16, so not only the CP0_Config1 had to be fixed (see previous patch), but also MIPS16 instructions must not be executed. (Hint from Nathan Froyd, thanks). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: fix user-mode emulation startupNathan Froyd2-8/+8
Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: set Config1.CA for MIPS16-aware CPUsNathan Froyd1-9/+18
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add copyright notice for mips16 workNathan Froyd2-1/+1
Also cross off mips16 ASE in TODO. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add mips16 instruction decodingNathan Froyd1-9/+1063
There's no good way to add this incrementally, so we do it all at once. The only changes to shared code are in handle_delay_slot. We need to flip ISAMode when doing a jump-and-exchange. We also need to set ISAMode the low bit of the target address for jump-to-register. Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT, make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want basic information about a branch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add enums for MIPS16 opcodesNathan Froyd1-0/+112
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: split out delay slot handlingNathan Froyd1-55/+79
Move delay slot handling to common code whose invocation can be controlled from gen_intermediate_code_internal. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add gen_base_offset_addrNathan Froyd1-24/+16
This is a common pattern in existing code. We'll also use it to implement the mips16 SAVE/RESTORE instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: make gen_compute_branch 16/32-bit-awareNathan Froyd1-7/+8
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: move ROTR and ROTRV inside gen_shift_{imm, }Nathan Froyd1-139/+148
It's easier to implement mips16 shift instructions if we're not examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV and do the special-case handling of SRL and SRLV inside decode_opc. Likewise for their 64-bit counterparts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: change interrupt bits to be mips16-awareNathan Froyd2-24/+44
We need to stash the operating mode into the low bit of the error PC and restore it on return from interrupts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add new HFLAGs for JALX and 16/32-bit delay slotsNathan Froyd1-19/+28
We create separate masks for the "basic" branch hflags and the "extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or of those two. This is done to avoid churning the codebase in lots of different places. We also make the execution mode an hflag under MIPS_HFLAG_TMASK Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: use physical address in lladdrAurelien Jarno3-28/+61
Currently the ll/sc instructions use the virtual address in both user and system mode. Use the physical address insteead in system mode. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: add a function to do virtual -> physical translationsAurelien Jarno2-0/+25
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: split code raising MMU exception in a separate functionAurelien Jarno1-46/+53
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: factorize load/store code in op_helper.cAurelien Jarno1-152/+100
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22target-mips: fix physical address type in MMU functionsAurelien Jarno2-11/+11
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno5-4/+49
Depending on the CPU, CP0_LLAddr is either read-only or read-write, and the returned value can be shifted by a variable amount of bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22target-mips: rename CP0_LLAddr into lladdrAurelien Jarno4-16/+16
The variable CP0_LLAddr represent the full lladdr, not the actual register value, which is only part of this value and depends on the CPU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14target-mips: fix indentationAurelien Jarno2-3/+3
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14mips: fix cpu_reset memory leakBlue Swirl3-56/+54
Remove cpu_mips_register() - move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init() - move the other parts in cpu_mips_init() Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori5-27/+28
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc5-28/+27
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-30target-mips: make sure constants are in the second argumentAurelien Jarno1-7/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30mips: Fix spelling in commentStefan Weil1-2/+2
inofficial -> unofficial Thanks to Blue Swirl. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-30target-mips: unmatched brackets in if 0Michael S. Tsirkin1-1/+0
Fix unmatched braket in commented out code Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-28target-mips: log instructions start in TCG codeAurelien Jarno1-0/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-23target-mips: remove MAX_OP_PER_INSTR workaroundAurelien Jarno1-2/+1
Now that MAX_OP_PER_INSTR has been increased to a safer value, removed the target-mips specific workaround. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-21Add 'static' to please SparseBlue Swirl1-1/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-14target-mips: fix single-steppingNathan Froyd1-3/+18
Single-stepping branches on MIPS didn't work right, because the generation of EXCP_DEBUG happened after the generation of the code to exit the current TB. That is, given the code: bne v0,v1,target nop ... target: addu v0,v0,v1 1: when you single-stepped through the NOP, execution wouldn't actually halt until you reached the label `1'. This patch corrects that and also changes single-stepping so that a branch and its delay slot are executed as one instruction for the purposes of single-stepping. This behavior is comparable to what other MIPS tools (e.g. MIPSsim with MDI) do. GDB avoids placing breakpoints in branch delay slots, so this change doesn't break anything on the GDB side. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-12Fix sys-queue.h conflict for goodBlue Swirl1-2/+2
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-25target-mips: fix conditional moves off fp condition codesNathan Froyd1-5/+5
Conditional moves off fp condition codes were using the result of get_fp_bit to isolate and test the relevant condition code. However, get_fp_bit returns the bit number of the condition code, not a bitmask. (Compare the use of get_fp_bit in gen_compute_branch1, for instance.) Fixed by shifting a bitmask into place using the result of get_fp_bit in the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}). Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-08-24cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd1-0/+1
handle_cpu_signal is very nearly copy-paste code for each target, with a few minor variations. This patch sets up appropriate defaults for a generic handle_cpu_signal and provides overrides for particular targets that did things differently. Fixing things like the persistent (XXX: use sigsetjmp) should now become somewhat easier. Previous comments on this patch suggest that the "activate soft MMU for this block" comments refer to defunct functionality. I have removed such blocks for the appropriate targets in this patch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela1-1/+1
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}Juan Quintela1-1/+1
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl4-8/+4
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-12target-mips: remove useless code in gen_st_cond()Aurelien Jarno1-1/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12Fix MIPS SCPaul Brook1-2/+2
Fix botched merge of op_ldst_sc calls to match actual implementation. Thanks to Aurelien Jarno for diagnosing this. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09MIPS atomic instructionsPaul Brook2-24/+64
Implement MIPS ll/sc instructions using atomic compare+exchange. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09MIPS usermode TLS registerPaul Brook1-0/+5
Implement cpu_set_tls for MIPS. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-03target-mips: fix MADD and MSUB/MSUBU instructionsNathan Froyd1-3/+3
MADD was not correctly writing to HI. MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-06-13Fix a warning: uint_fast8_t is not 8 bits on OpenBSD/Sparc64Blue Swirl1-2/+6
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-21Convert machine registration to use module init functionsAnthony Liguori1-9/+0
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-19Hardware convenience libraryPaul Brook1-3/+0
The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13Replace gcc variadic macro extension with C99 versionBlue Swirl1-3/+3
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-04target-mips: proper sign extension for 'SUBU rd, zero, rt'Aurelien Jarno1-0/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-04target-mips: fix comments about SUB/DSUBAurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori1-0/+1
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
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