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target-mips
Age
Commit message (
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)
Author
Files
Lines
2007-05-08
Work around gcc's mips define, spotted by Stefan Weil.
ths
1
-12
/
+12
2007-05-07
MIPS 64-bit FPU support, plus some collateral bugfixes in the
ths
9
-518
/
+1700
2007-05-07
Update TODO.
ths
1
-4
/
+3
2007-05-07
Clear BD slot on next exception if appropriate.
ths
1
-0
/
+4
2007-05-05
Fix a really stupid bug in the [ls]d[lr] emulation, by Herve Poussineau.
ths
1
-3
/
+3
2007-04-29
Kill broken host register definitions, thanks to Paul Brook and Herve
ths
2
-13
/
+4
2007-04-29
Revert last checkin.
ths
1
-1
/
+1
2007-04-29
Hopefully the final fix for LUI sign extensions.
ths
1
-1
/
+1
2007-04-28
Update TODO.
ths
1
-0
/
+9
2007-04-25
Next attempt to get the lui sign extension right.
ths
2
-3
/
+2
2007-04-25
Fix lui sign extension.
ths
1
-1
/
+1
2007-04-19
Update comment. We can't easily adhere to the architecture spec because
ths
1
-3
/
+3
2007-04-17
Choose number of TLBs at runtime, by Herve Poussineau.
ths
6
-26
/
+25
2007-04-16
Simplify branch likely handling.
ths
1
-6
/
+8
2007-04-15
Don't use T2 for INS, it conflicts with branch delay slot handling.
ths
2
-6
/
+6
2007-04-15
Fix qemu SIGFPE caused by division-by-zero due to underflow.
ths
3
-13
/
+28
2007-04-15
Small code generation optimization.
ths
1
-3
/
+6
2007-04-15
Delete unused define.
ths
1
-2
/
+0
2007-04-14
Restart interrupts after an exception.
ths
2
-9
/
+33
2007-04-13
Nicer Log formatting.
ths
1
-1
/
+1
2007-04-13
Another fix for CP0 Cause register handling.
ths
2
-2
/
+2
2007-04-11
Make SYNCI_Step and CCRes CPU-specific.
ths
2
-3
/
+16
2007-04-11
Throw RI for invalid MFMC0-class instructions. Introduce optional
ths
2
-3
/
+18
2007-04-11
Code formatting fix.
ths
1
-935
/
+938
2007-04-11
More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may
ths
2
-10
/
+10
2007-04-09
Fix CP0_IntCtl handling.
ths
2
-2
/
+6
2007-04-09
Proper handling of reserved bits in the context register.
ths
1
-1
/
+1
2007-04-09
Mark watchpoint features as unimplemented.
ths
2
-3
/
+9
2007-04-09
Catch unaligned sc/scd.
ths
2
-0
/
+10
2007-04-09
Fix exception handling cornercase for rdhwr.
ths
2
-37
/
+9
2007-04-09
Remove bogus mtc0 handling.
ths
1
-10
/
+0
2007-04-07
Unify IRQ handling.
pbrook
1
-0
/
+2
2007-04-07
cpu_get_phys_page_debug should return target_phys_addr_t
j_mayer
1
-2
/
+2
2007-04-07
Implement prefx.
ths
1
-1
/
+41
2007-04-07
Set proper BadVAddress value for unaligned instruction fetch.
ths
1
-1
/
+2
2007-04-07
Actually skip over delay slot for a non-taken branch likely.
ths
1
-2
/
+2
2007-04-07
Fix ins/ext cornercase.
ths
1
-4
/
+4
2007-04-06
Fix handling of ADES exceptions.
ths
1
-1
/
+3
2007-04-06
Save state for all CP0 instructions, they may throw a CPU exception.
ths
3
-16
/
+45
2007-04-05
fix branch delay slot cornercases.
ths
2
-3
/
+6
2007-04-05
Fix rotr immediate ops, mask shift/rotate arguments to their allowed
ths
3
-48
/
+103
2007-04-05
Handle EBase properly.
ths
1
-1
/
+1
2007-04-05
Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise
ths
2
-92
/
+131
2007-04-05
64bit MIPS FPUs have 32 registers.
ths
1
-2
/
+1
2007-04-04
Fix code formatting.
ths
1
-66
/
+66
2007-04-02
MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers
ths
1
-2
/
+9
2007-04-02
Build fix for 64bit machines. (This is still not correct mul/div handling.)
ths
1
-6
/
+12
2007-04-01
Actually enable 64bit configuration.
ths
8
-38
/
+35
2007-04-01
MIPS64 configurations.
ths
1
-2
/
+0
2007-03-31
Malta CBUS UART support.
ths
1
-1
/
+1
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