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path: root/target-mips/translate_init.c
AgeCommit message (Expand)AuthorFilesLines
2016-09-23target-mips: add 24KEc CPU definitionAndré Draszik1-0/+22
2016-07-12target-mips: enable 10-bit ASIDs in I6400 CPULeon Alrae1-1/+1
2016-07-12target-mips: replace MIPS64R6-generic with the real I6400 CPU modelLeon Alrae1-11/+9
2016-06-24target-mips: Implement FCR31's R/W bitmask and related functionalitiesAleksandar Markovic1-0/+26
2016-06-24target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSAAleksandar Markovic1-1/+2
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic1-0/+2
2016-03-30target-mips: add MAAR, MAARI registerYongbok Kim1-1/+2
2016-03-30target-mips: enable CM GCR in MIPS64R6-generic CPULeon Alrae1-1/+2
2016-03-23target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUsLeon Alrae1-9/+13
2016-02-26target-mips: implement R6 multi-threadingYongbok Kim1-1/+2
2015-10-30target-mips: Set Config5.XNP for R6 coresYongbok Kim1-2/+2
2015-08-13target-mips: update mips32r5-generic into P5600Yongbok Kim1-24/+29
2015-07-15target-mips: fix MIPS64R6-generic configurationYongbok Kim1-9/+9
2015-06-26target-mips: add mips32r6-generic CPU definitionYongbok Kim1-0/+37
2015-06-12target-mips: enable XPA and LPA featuresLeon Alrae1-6/+10
2015-06-12target-mips: remove misleading comments in translate_init.cLeon Alrae1-9/+0
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-1/+2
2015-06-11target-mips: Misaligned memory accesses for R6Yongbok Kim1-1/+1
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-4/+5
2015-03-11target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae1-8/+2
2015-02-13target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processorsMaciej W. Rozycki1-2/+2
2014-12-16target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki1-19/+21
2014-12-16target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki1-0/+41
2014-12-16target-mips: Add 5KEc and 5KEf MIPS64r2 processorsMaciej W. Rozycki1-0/+45
2014-11-07mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bitsMaciej W. Rozycki1-3/+5
2014-11-03target-mips: add MSA support to mips32r5-genericYongbok Kim1-2/+2
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim1-0/+34
2014-11-03target-mips: enable features in MIPS64R6-generic CPULeon Alrae1-2/+9
2014-11-03target-mips: add TLBINV supportLeon Alrae1-0/+2
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-0/+2
2014-10-14target-mips: define a new generic CPU supporting MIPS64 Release 6 ISALeon Alrae1-0/+30
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell1-11/+11
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-1/+3
2014-02-10target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic1-4/+5
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic1-1/+11
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic1-1/+8
2014-02-10target-mips: add CPU definition for MIPS32R5Petar Jovanovic1-0/+25
2013-08-03target-mips: fix 34Kf configuration for DSP ASEYongbok Kim1-4/+3
2012-10-31target-mips: Add ASE DSP processorsJia Liu1-0/+52
2011-09-06mips: Default to using one VPE and one TC.Edgar E. Iglesias1-1/+1
2011-09-06mips: Enable VInt interrupt mode for the 34KfEdgar E. Iglesias1-1/+1
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-2/+2
2011-05-08Fix typos in comments (interupt -> interrupt)Stefan Weil1-1/+1
2011-05-06Fix typo in code and commentsStefan Weil1-1/+1
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-1/+1
2010-07-31Remove unused constantHervé Poussineau1-4/+0
2010-06-29MIPS: Initial support of fulong mini pc (CPU definition)Huacai Chen1-0/+35
2009-12-17target-mips: No MIPS16 support for 4Kc, 4KEc coresStefan Weil1-3/+3
2009-12-16target-mips: 4Kc, 4KEc cores do not support MIPS16Stefan Weil1-3/+3
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