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path: root/target-mips/translate.c
AgeCommit message (Expand)AuthorFilesLines
2012-11-24target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)1-0/+17
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-15target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)1-1/+1
2012-11-11target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson1-7/+11
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-10-31target-mips: use deposit instead of hardcoded versionAurelien Jarno1-28/+4
2012-10-31target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno1-48/+37
2012-10-31target-mips: implement movn/movz using movcondAurelien Jarno1-15/+12
2012-10-31target-mips: don't use local temps for store conditionalAurelien Jarno1-5/+6
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno1-13/+62
2012-10-31target-mips: optimize load operationsAurelien Jarno1-4/+12
2012-10-31target-mips: cleanup load/store operationsAurelien Jarno1-64/+35
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno1-12/+12
2012-10-31target-mips: do not save CPU state when using retranslationAurelien Jarno1-20/+0
2012-10-31target-mips: correctly restore btarget upon exceptionAurelien Jarno1-0/+11
2012-10-31target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno1-36/+0
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu1-0/+351
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu1-0/+350
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu1-0/+249
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu1-0/+485
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu1-0/+324
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu1-3/+792
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu1-0/+88
2012-10-31target-mips: Add ASE DSP branch instructionsJia Liu1-0/+36
2012-10-31Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu1-27/+95
2012-10-31target-mips: Add ASE DSP resources access checkJia Liu1-0/+23
2012-10-28target-mips: Use TCG registers for the FPU.Richard Henderson1-42/+54
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
2012-09-19target-mips: Implement Loongson Multimedia InstructionsRichard Henderson1-3/+376
2012-09-19target-mips: Always evaluate debugging macro argumentsRichard Henderson1-14/+17
2012-09-19target-mips: Fix MIPS_DEBUG.Richard Henderson1-36/+38
2012-09-19target-mips: Set opn in gen_ldst_multiple.Richard Henderson1-0/+6
2012-09-15target-mips: switch to AREG0 free modeBlue Swirl1-368/+386
2012-09-08MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki1-13/+3
2012-08-27target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson1-1/+9
2012-08-27target-mips: add privilege level check to several Cop0 instructionsEric Johnson1-0/+9
2012-08-27mips-linux-user: Always support rdhwr.Richard Henderson1-0/+4
2012-08-27target-mips: Streamline indexed cp1 memory addressing.Richard Henderson1-2/+1
2012-08-27Fix order of CVT.PS.S operandsRichard Sandiford1-1/+1
2012-08-27Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford1-2/+2
2012-08-23target-mips: Enable access to required RDHWR hardware registersMeador Inge1-2/+3
2012-08-09MIPS: Correct FCR0 initializationNathan Froyd1-0/+1
2012-06-04target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber1-2/+2
2012-06-04target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber1-1/+1
2012-05-19mips: Fix BC1ANY[24]F instructionsRichard Sandiford1-4/+4
2012-04-30target-mips: Start QOM'ifying CPU initAndreas Färber1-1/+0
2012-04-30target-mips: QOM'ify CPUAndreas Färber1-1/+3
2012-03-14target-mips: Don't overuse CPUStateAndreas Färber1-178/+178
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber1-2/+2
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