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2009-12-13target-mips: fix user-mode emulation startupNathan Froyd1-0/+8
Running programs with the MIPS user-mode emulator fails during dynamic loading, as floating-point instructions are not enabled in in env->hflags. Move the code for doing so from fpu_init to cpu_reset so the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset setting env->hflags to MIPS_HFLAG_UM. The same end can be achieved by swapping the ordering of fpu_init and cpu_reset in cpu_mips_init, but it seemed better to consolidate the CONFIG_USER_ONLY code into a single location. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add copyright notice for mips16 workNathan Froyd1-0/+1
Also cross off mips16 ASE in TODO. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add mips16 instruction decodingNathan Froyd1-9/+1063
There's no good way to add this incrementally, so we do it all at once. The only changes to shared code are in handle_delay_slot. We need to flip ISAMode when doing a jump-and-exchange. We also need to set ISAMode the low bit of the target address for jump-to-register. Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT, make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want basic information about a branch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add enums for MIPS16 opcodesNathan Froyd1-0/+112
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: split out delay slot handlingNathan Froyd1-55/+79
Move delay slot handling to common code whose invocation can be controlled from gen_intermediate_code_internal. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: add gen_base_offset_addrNathan Froyd1-24/+16
This is a common pattern in existing code. We'll also use it to implement the mips16 SAVE/RESTORE instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: make gen_compute_branch 16/32-bit-awareNathan Froyd1-7/+8
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13target-mips: move ROTR and ROTRV inside gen_shift_{imm, }Nathan Froyd1-139/+148
It's easier to implement mips16 shift instructions if we're not examining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRV and do the special-case handling of SRL and SRLV inside decode_opc. Likewise for their 64-bit counterparts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30target-mips: use physical address in lladdrAurelien Jarno1-28/+13
Currently the ll/sc instructions use the virtual address in both user and system mode. Use the physical address insteead in system mode. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno1-2/+5
Depending on the CPU, CP0_LLAddr is either read-only or read-write, and the returned value can be shifted by a variable amount of bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22target-mips: rename CP0_LLAddr into lladdrAurelien Jarno1-6/+6
The variable CP0_LLAddr represent the full lladdr, not the actual register value, which is only part of this value and depends on the CPU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14target-mips: fix indentationAurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14mips: fix cpu_reset memory leakBlue Swirl1-4/+51
Remove cpu_mips_register() - move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init() - move the other parts in cpu_mips_init() Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-2/+2
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-2/+2
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-30target-mips: make sure constants are in the second argumentAurelien Jarno1-7/+7
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30mips: Fix spelling in commentStefan Weil1-2/+2
inofficial -> unofficial Thanks to Blue Swirl. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-28target-mips: log instructions start in TCG codeAurelien Jarno1-0/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-23target-mips: remove MAX_OP_PER_INSTR workaroundAurelien Jarno1-2/+1
Now that MAX_OP_PER_INSTR has been increased to a safer value, removed the target-mips specific workaround. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-14target-mips: fix single-steppingNathan Froyd1-3/+18
Single-stepping branches on MIPS didn't work right, because the generation of EXCP_DEBUG happened after the generation of the code to exit the current TB. That is, given the code: bne v0,v1,target nop ... target: addu v0,v0,v1 1: when you single-stepped through the NOP, execution wouldn't actually halt until you reached the label `1'. This patch corrects that and also changes single-stepping so that a branch and its delay slot are executed as one instruction for the purposes of single-stepping. This behavior is comparable to what other MIPS tools (e.g. MIPSsim with MDI) do. GDB avoids placing breakpoints in branch delay slots, so this change doesn't break anything on the GDB side. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-12Fix sys-queue.h conflict for goodBlue Swirl1-2/+2
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-25target-mips: fix conditional moves off fp condition codesNathan Froyd1-5/+5
Conditional moves off fp condition codes were using the result of get_fp_bit to isolate and test the relevant condition code. However, get_fp_bit returns the bit number of the condition code, not a bitmask. (Compare the use of get_fp_bit in gen_compute_branch1, for instance.) Fixed by shifting a bitmask into place using the result of get_fp_bit in the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}). Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-12target-mips: remove useless code in gen_st_cond()Aurelien Jarno1-1/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12Fix MIPS SCPaul Brook1-2/+2
Fix botched merge of op_ldst_sc calls to match actual implementation. Thanks to Aurelien Jarno for diagnosing this. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09MIPS atomic instructionsPaul Brook1-24/+59
Implement MIPS ll/sc instructions using atomic compare+exchange. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-03target-mips: fix MADD and MSUB/MSUBU instructionsNathan Froyd1-3/+3
MADD was not correctly writing to HI. MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-13Replace gcc variadic macro extension with C99 versionBlue Swirl1-3/+3
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-04target-mips: proper sign extension for 'SUBU rd, zero, rt'Aurelien Jarno1-0/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-05-04target-mips: fix comments about SUB/DSUBAurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori1-0/+1
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-20Enable access to SYNCI_Step register in usermode emulation.pbrook1-0/+2
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7191 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17Revert "target-mips: fix call to check_*() functions"aurel321-24/+12
This reverts commit r7127, r7132 is a better fix for that. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7133 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-17target-mips: simplify exception generationaurel321-4/+0
There is no need to exit the tb after a call to helper_raise_exception as it already calls cpu_loop_exit(). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7132 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16target-mips: fix revision r7126aurel321-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7128 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16target-mips: fix call to check_*() functionsaurel321-12/+24
check_*() functions may in fine call generate_exception(), which ends by a call to tcg_gen_exit_tb(). As a consequence, we have to make sure that no TCG temp variables are crossing a check_*() function. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7127 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16target-mips: optimize gen_flt3_ldst()aurel321-4/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7126 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16target-mips: optimize gen_flt_ldst()aurel321-4/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7125 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16Stop translation after a syscall instruciton.pbrook1-0/+1
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7124 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-15target-mips: mark zero register as unused.aurel321-0/+1
Suggested by Stuart Brady. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7107 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-15target-mips: variable names consistencyaurel321-402/+404
Use a consistent naming of arguments and TCG variables across the whole file, the same as in tcg/tcg-op.h: - arg1, arg2, ... for arguments - t0, t1, t2, ... for variables Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7106 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13target-mips: fix commits 7040 and 7042aurel321-2/+6
CPU state should also be saved for helpers that in fine call cpu_unlink_tb(). Reported by Stefan Weil. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7096 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-12target-mips: fix commit 7046aurel321-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7095 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11target-mips: don't map zero register as a TCG globalaurel321-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7094 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11target-mips: optimize gen_ldst()aurel321-22/+64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7093 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11target-mips: optimize gen_arith_imm()aurel321-106/+161
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7092 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-10target-mips: fix commit r7076aurel321-2/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7078 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-10target-mips: optimize gen_movcf_d()aurel321-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7077 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-10target-mips: optimize a few tcg_temp_free()aurel321-3/+3
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7076 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-08target-mips: optimize gen_farith()aurel321-56/+47
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7046 c046a42c-6fe2-441c-8c8c-71466251a162
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