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path: root/target-mips/translate.c
AgeCommit message (Expand)AuthorFilesLines
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson1-5/+3
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson1-1/+1
2015-02-10target-mips: Clean up switch fall through after commit fecd264Markus Armbruster1-0/+4
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini1-1/+1
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini1-10/+14
2014-12-16target-mips: convert single case switch into if statementLeon Alrae1-3/+1
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-0/+2
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki1-5/+14
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki1-9/+98
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki1-2/+6
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki1-0/+4
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki1-3/+3
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki1-1/+2
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki1-5/+8
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki1-1/+1
2014-11-07target-mips: fix multiple TCG registers covering same dataYongbok Kim1-5/+3
2014-11-07mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki1-1/+1
2014-11-07target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae1-0/+1
2014-11-07mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki1-2/+7
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim1-1/+48
2014-11-03target-mips: add MSA 2RF format instructionsYongbok Kim1-0/+74
2014-11-03target-mips: add MSA VEC/2R format instructionsYongbok Kim1-0/+113
2014-11-03target-mips: add MSA 3RF format instructionsYongbok Kim1-0/+163
2014-11-03target-mips: add MSA ELM format instructionsYongbok Kim1-0/+118
2014-11-03target-mips: add MSA 3R format instructionsYongbok Kim1-0/+242
2014-11-03target-mips: add MSA BIT format instructionsYongbok Kim1-0/+88
2014-11-03target-mips: add MSA I5 format instructionYongbok Kim1-0/+77
2014-11-03target-mips: add MSA I8 format instructionsYongbok Kim1-2/+80
2014-11-03target-mips: add MSA branch instructionsYongbok Kim1-114/+220
2014-11-03target-mips: add msa_reset(), global msa registerYongbok Kim1-0/+56
2014-11-03target-mips: add MSA opcode enumYongbok Kim1-0/+245
2014-11-03target-mips: stop translation after ctc1Yongbok Kim1-0/+6
2014-11-03target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae1-278/+260
2014-11-03target-mips: implement forbidden slotLeon Alrae1-35/+74
2014-11-03target-mips: add Config5.SBRILeon Alrae1-1/+23
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae1-6/+70
2014-11-03target-mips: add TLBINV supportLeon Alrae1-0/+22
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-2/+24
2014-11-03target-mips: add KScratch registersLeon Alrae1-0/+44
2014-10-14target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell1-19/+1
2014-10-14target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell1-0/+2
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim1-182/+116
2014-10-14target-mips/translate.c: Update OPC_SYNCIDongxue Zhang1-1/+6
2014-10-14target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim1-2/+16
2014-10-14target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae1-0/+6
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim1-2/+204
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae1-44/+397
2014-10-14target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae1-14/+189
2014-10-13target-mips: add compact and CP1 branchesYongbok Kim1-14/+459
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