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path: root/target-mips/translate.c
AgeCommit message (Expand)AuthorFilesLines
2007-05-11Improved debug output for the MIPS opcode decoder.ths1-85/+77
2007-05-10Fix for the scd instruction, by Aurelien Jarno.ths1-0/+1
2007-05-09Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths1-2/+2
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-243/+824
2007-04-25Next attempt to get the lui sign extension right.ths1-2/+1
2007-04-25Fix lui sign extension.ths1-1/+1
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-4/+0
2007-04-16Simplify branch likely handling.ths1-6/+8
2007-04-15Don't use T2 for INS, it conflicts with branch delay slot handling.ths1-4/+4
2007-04-15Small code generation optimization.ths1-3/+6
2007-04-14Restart interrupts after an exception.ths1-8/+19
2007-04-11Make SYNCI_Step and CCRes CPU-specific.ths1-3/+0
2007-04-11Throw RI for invalid MFMC0-class instructions. Introduce optionalths1-3/+13
2007-04-11Code formatting fix.ths1-935/+938
2007-04-11More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths1-1/+5
2007-04-09Fix CP0_IntCtl handling.ths1-0/+3
2007-04-09Mark watchpoint features as unimplemented.ths1-0/+1
2007-04-09Catch unaligned sc/scd.ths1-0/+2
2007-04-09Fix exception handling cornercase for rdhwr.ths1-11/+5
2007-04-09Remove bogus mtc0 handling.ths1-10/+0
2007-04-07Implement prefx.ths1-1/+41
2007-04-07Set proper BadVAddress value for unaligned instruction fetch.ths1-1/+2
2007-04-07Actually skip over delay slot for a non-taken branch likely.ths1-2/+2
2007-04-06Save state for all CP0 instructions, they may throw a CPU exception.ths1-0/+1
2007-04-05fix branch delay slot cornercases.ths1-2/+5
2007-04-05Fix rotr immediate ops, mask shift/rotate arguments to their allowedths1-33/+93
2007-04-05Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths1-73/+82
2007-04-04Fix code formatting.ths1-66/+66
2007-04-02MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths1-2/+9
2007-04-01Actually enable 64bit configuration.ths1-17/+17
2007-03-30Sanitize mips exception handling.ths1-19/+3
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths1-23/+43
2007-03-21Move mips CPU specific initialization to translate_init.c.ths1-3/+0
2007-03-19Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.ths1-5/+13
2007-03-19Define gen_intermediate_code_internal as "static inline".ths1-2/+3
2007-03-18MIPS -cpu selection support, by Herve Poussineau.ths1-7/+2
2007-03-02MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths1-0/+6
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths1-74/+60
2007-02-27Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths1-29/+16
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths1-19/+19
2007-01-24EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths1-3/+3
2007-01-23Implementing dmfc/dmtc.ths1-2/+1203
2006-12-21Scrap SIGN_EXTEND32.ths1-3/+3
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths1-39/+54
2006-12-16Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto.ths1-0/+1
2006-12-10Handle invalid accesses as SIGILL for mips/mipsel userland emulation.ths1-0/+3
2006-12-07Fix build of MIPS target without FPU support.ths1-0/+24
2006-12-07Fix reset handling, CP0 isn't enabled by default (a fact which doesn'tths1-3/+11
2006-12-07Simplify mask construction.ths1-2/+2
2006-12-06Update copyright notice.ths1-0/+1