| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2008-06-09 | Switch remaining CP0 instructions to TCG or helper functions. | ths | 1 | -244/+272 |
| 2008-06-08 | Register helper functions. | ths | 1 | -0/+5 |
| 2008-06-05 | Free constant temporaries. | ths | 1 | -2/+20 |
| 2008-06-04 | Explicitly free temporaries. | ths | 1 | -160/+130 |
| 2008-06-04 | Remove the temporaries cache of the MIPS target. | ths | 1 | -83/+46 |
| 2008-06-04 | Fix pointer calculation for MIPS64 targets. | ths | 1 | -6/+6 |
| 2008-06-04 | Delete duplicate code. | ths | 1 | -3/+0 |
| 2008-06-02 | Fix type mismatch. | ths | 1 | -2/+2 |
| 2008-06-02 | Fix argument order. | ths | 1 | -2/+2 |
| 2008-06-02 | Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford. | ths | 1 | -2/+7 |
| 2008-05-30 | Fix for 32-bit MIPS. | ths | 1 | -9/+10 |
| 2008-05-29 | Avoid qemu SIGFPE for MIPS DIV, by Richard Sandiford. | ths | 1 | -14/+10 |
| 2008-05-29 | Fix truncate/extend reversal in MIPS DIV{, U} handling, by Richard Sandiford. | ths | 1 | -8/+8 |
| 2008-05-29 | Fix modulus result from MIPS DDIV & avoid overflowing division, | ths | 1 | -9/+14 |
| 2008-05-28 | Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford. | ths | 1 | -45/+44 |
| 2008-05-24 | Fix mov[tf].ps handling for MIPS, by Richard Sandiford. | ths | 1 | -2/+4 |
| 2008-05-24 | Un-break MIPS conditional moves, by Richard Sandiford. | ths | 1 | -15/+17 |
| 2008-05-24 | Fix ARM conditional branch bug. | pbrook | 1 | -24/+24 |
| 2008-05-23 | Swithc some MIPS CP0 accesses to TCG. | ths | 1 | -97/+194 |
| 2008-05-23 | Switch MIPS movf/movt to TCG. | ths | 1 | -8/+22 |
| 2008-05-22 | Switch MIPS branch handling to TCG, and clean out pointless wrapper | ths | 1 | -394/+286 |
| 2008-05-21 | Switch MIPS clo/clz and the condition tests to TCG. | ths | 1 | -6/+65 |
| 2008-05-21 | Switch MIPS movn/movz to TCG. | ths | 1 | -2/+14 |
| 2008-05-18 | Switch most MIPS logical and arithmetic instructions to TCG. | ths | 1 | -85/+424 |
| 2008-05-18 | Fix local register cache handling. | ths | 1 | -4/+13 |
| 2008-05-07 | Be more economical with local temporaries. | ths | 1 | -2/+44 |
| 2008-05-06 | Convert some MIPS load/store instructions to TCG. | ths | 1 | -51/+175 |
| 2008-05-06 | Use TCG for MIPS GPR moves. | ths | 1 | -40/+78 |
| 2008-05-06 | Fix MIPS64 branches. Funny how this survived testing. | ths | 1 | -1/+1 |
| 2008-05-05 | Really really revert commit r4343 | aurel32 | 1 | -0/+4 |
| 2008-05-05 | Really revert commit r4343 | aurel32 | 1 | -2/+0 |
| 2008-05-05 | Don't stop translation for mtc0 compare | aurel32 | 1 | -2/+0 |
| 2008-05-04 | Simplify mips branch handling. Retire T2 from use. Use TCG for branches. | ths | 1 | -29/+48 |
| 2008-04-28 | Factorize code in translate.c | aurel32 | 1 | -0/+8 |
| 2008-04-11 | Remove osdep.c/qemu-img code duplication | aurel32 | 1 | -0/+1 |
| 2008-02-12 | Make MIPS MT implementation more cache friendly. | ths | 1 | -8/+8 |
| 2008-02-01 | use the TCG code generator | bellard | 1 | -37/+6 |
| 2007-12-30 | MIPS COP1X (and related) instructions, by Richard Sandiford. | ths | 1 | -9/+47 |
| 2007-12-25 | Support for VR5432, and some of its special instructions. Original patch | ths | 1 | -1/+100 |
| 2007-12-24 | Update debug code to match new accumulator register layout. | ths | 1 | -4/+4 |
| 2007-12-09 | Handle cpu_model in copy_cpu(), by Kirill A. Shutemov. | ths | 1 | -0/+1 |
| 2007-11-26 | Micro-optimize back-to-back store-load sequences. | ths | 1 | -103/+135 |
| 2007-11-22 | Optimize the conventional move operation. | ths | 1 | -0/+6 |
| 2007-11-18 | Fix MIPS64 R2 instructions. | ths | 1 | -6/+13 |
| 2007-11-10 | added cpu_model parameter to cpu_init() | bellard | 1 | -3/+10 |
| 2007-11-08 | Clean out the N32 macros from target-mips, and introduce MIPS ABI specific | ths | 1 | -27/+27 |
| 2007-11-08 | Formatting fix. | ths | 1 | -1/+1 |
| 2007-10-28 | Implement missing MIPS supervisor mode bits. | ths | 1 | -5/+7 |
| 2007-10-24 | Remove bogus instruction decode. | ths | 1 | -1/+0 |
| 2007-10-23 | Use the standard ASE check for MIPS-3D and MT. | ths | 1 | -92/+77 |
