aboutsummaryrefslogtreecommitdiff
path: root/target-mips/translate.c
AgeCommit message (Expand)AuthorFilesLines
2013-07-09target-mips: Change gen_intermediate_code_internal() argument to MIPSCPUAndreas Färber1-4/+5
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-2/+4
2013-05-08target-mips: add missing check_dspr2 for multiply instructionsPetar Jovanovic1-0/+1
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-2/+2
2013-03-05mips64-linux-user: Enable 64-bit address mode and fpuRichard Henderson1-0/+12
2013-03-05target-mips: Fix accumulator selection for MIPS16 and microMIPSRichard Sandiford1-84/+64
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
2013-02-23target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson1-28/+20
2013-02-16target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber1-2/+1
2013-02-16target-mips: Introduce QOM realizefn for MIPSCPUAndreas Färber1-2/+3
2013-01-31target-mips: enable access to DSP ASE if implementedPetar Jovanovic1-4/+2
2013-01-31target-mips: Sign-extend the result of LWRRichard Sandiford1-0/+1
2013-01-31target-mips: Fix signedness of loads in MIPS16 RESTOREsRichard Sandiford1-1/+1
2013-01-31target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno1-46/+87
2013-01-31target-mips: generate a reserved instruction exception on CPU without DSPAurelien Jarno1-2/+10
2013-01-31target-mips: copy insn_flags in DisasContextAurelien Jarno1-381/+381
2013-01-31target-mips: fix DSP loads with rd = 0Aurelien Jarno1-5/+0
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber1-10/+7
2013-01-01target-mips: Make repl_ph to sign extend to target-longJovanovic, Petar1-1/+2
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini1-1/+1
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin1-3/+3
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin1-1/+1
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin1-2/+2
2012-11-24target-mips: remove POOL48A from the microMIPS decodingAurelien Jarno1-1/+0
2012-11-24target-mips: Clean up microMIPS32 major opcode陳韋任 (Wei-Ren Chen)1-7/+17
2012-11-24target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)1-0/+17
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin1-3/+3
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin1-4/+5
2012-11-15target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)1-1/+1
2012-11-11target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson1-7/+11
2012-11-10disas: avoid using cpu_single_envBlue Swirl1-1/+1
2012-10-31target-mips: use deposit instead of hardcoded versionAurelien Jarno1-28/+4
2012-10-31target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno1-48/+37
2012-10-31target-mips: implement movn/movz using movcondAurelien Jarno1-15/+12
2012-10-31target-mips: don't use local temps for store conditionalAurelien Jarno1-5/+6
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno1-13/+62
2012-10-31target-mips: optimize load operationsAurelien Jarno1-4/+12
2012-10-31target-mips: cleanup load/store operationsAurelien Jarno1-64/+35
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno1-12/+12
2012-10-31target-mips: do not save CPU state when using retranslationAurelien Jarno1-20/+0
2012-10-31target-mips: correctly restore btarget upon exceptionAurelien Jarno1-0/+11
2012-10-31target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno1-36/+0
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu1-0/+351
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu1-0/+350
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu1-0/+249
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu1-0/+485
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu1-0/+324
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu1-3/+792
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu1-0/+88
generated by cgit v1.1 at 2024-12-28 12:36:48 +0000