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2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae1-7/+12
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: support Page Frame Number Extension fieldLeon Alrae1-6/+26
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large physical address is not supported. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae1-4/+4
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-1/+11
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11target-mips: Misaligned memory accesses for MSAYongbok Kim1-66/+77
MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove unused do_* functions] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-0/+34
This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-02-13target-mips: ll and lld cause AdEL exception for unaligned addressLeon Alrae1-3/+7
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>
2015-01-20target-mips: Don't use _raw load/store accessorsPeter Maydell1-2/+2
Use cpu_*_data instead of the direct *_raw load/store accessors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1421334118-3287-9-git-send-email-peter.maydell@linaro.org
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-12/+0
Add missing calls to synchronise the SoftFloat status with the CP1.FSCR: + for the rounding and flush-to-zero modes upon processor reset, + for the flush-to-zero mode on FSCR updates through the GDB stub. Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE macro. Signed-off-by: Thomas Schwinge <thomas@codesourcery.com> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki1-1/+2
Make CP0.Status writes made with the MTTC0 instruction respect this register's mask just like all the other places. Also preserve the current values of masked out bits. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki1-0/+8
Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This bit is mandatory for any processor that implements the microMIPS instruction set. This bit is r/w for processors that implement both the standard MIPS and the microMIPS instruction set. This bit is r/o and hardwired to 1 if only the microMIPS instruction set is implemented. There is no other bit ever writable in CP0.Config3 so defining a corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I think an overkill. Therefore make the ability to write the bit rely on the presence of ASE_MICROMIPS set in the instruction flags. The read-only case of the microMIPS instruction set being implemented only can be added when we add support for such a configuration. We do not currently have such support, we have no instruction flag that would control the presence of the standard MIPS instruction set nor any associated code in instruction decoding. This change is needed to boot a microMIPS Linux kernel successfully, otherwise it hangs early on as interrupts are enabled and then the exception handler invoked loops as its first instruction is interpreted in the wrong execution mode and triggers another exception right away. And then over and over again. We already check the current setting of the CP0.Config3.ISAOnExc in `set_hflags_for_handler' to set the ISA bit correctly on the exception handler entry so it is the ability to set it that is missing only. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki1-84/+7
Make writes to CP0.Status and CP0.Cause have the same effect as executing corresponding MTC0 instructions would in Kernel Mode. Also ignore writes in the user emulation mode. Currently for requests from the GDB stub we write all the bits across both registers, ignoring any read-only locations, and do not synchronise the environment to evaluate side effects. We also write these registers in the user emulation mode even though a real kernel presents them as read only. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki1-2/+4
Correct these issues with the handling of CP0.Status for MIPSr6: * only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that is for processors that do implement Supervisor Mode, let the bit pattern be written to CP0.Status.UM:R0 freely (of course the value written to read-only CP0.Status.R0 will be discarded anyway); this is in accordance to the relevant architecture specification[1], * check the newly written pattern rather than the current contents of CP0.Status for the KSU bits being 0b11, * use meaningful macro names to refer to CP0.Status bits rather than magic numbers. References: [1] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64 Privileged Resource Architecture", MIPS Technologies, Inc., Document Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 "Status Register Field Descriptions", pp. 210-211. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Restore the order of helpersMaciej W. Rozycki1-159/+160
Restore the order of helpers that used to be: unary operations (generic, then MIPS-specific), binary operations (generic, then MIPS-specific), compare operations. At one point FMA operations were inserted at a random place in the file, disregarding the preexisting order, and later on even more operations sprinkled across the file. Revert the mess by moving FMA operations to a new ternary class inserted after the binary class and move the misplaced unary and binary operations to where they belong. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki1-2/+0
Remove the `FLOAT_OP' macro, unused since commit b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for the MIPS FPU emulation.]. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki1-1/+1
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the exception flag check, for consistency with the remaining helpers that do it last too. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA MI10 format instructionsYongbok Kim1-4/+80
add MSA MI10 format instructions update LSA and DLSA for MSA add 16, 64 bit load and store Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim1-2/+2
Remove the duplicated ieee_rm in gdbstub.c. Make the other ieee_rm and ieee_ex_to_mips available to other files. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add MSA defines and data structureYongbok Kim1-0/+1
add defines and data structure for MIPS SIMD Architecture Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add restrictions for possible values in registersLeon Alrae1-17/+53
In Release 6 not all the values are allowed to be written to a register. If the value is not valid or unsupported then it should stay unchanged. For pre-R6 the existing behaviour has been changed only for CP0_Index register as the current implementation does not seem to be correct - it looks like it tries to limit the input value but the limit is higher than the actual number of tlb entries. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae1-2/+15
BadInstr Register (CP0 Register 8, Select 1) The BadInstr register is a read-only register that capture the most recent instruction which caused an exception. BadInstrP Register (CP0 Register 8, Select 2) The BadInstrP register contains the prior branch instruction, when the faulting instruction is in a branch delay slot. Using error_code to indicate whether AdEL or TLBL was triggered during instruction fetch, in this case BadInstr is not updated as valid instruction word is not available. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add TLBINV supportLeon Alrae1-7/+58
For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-3/+22
PageGrain needs rw bitmask which differs between MIPS architectures. In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable, whereas in R6 they are read-only 1. On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward compatiblity, therefore there are separate mtc0 and dmtc0 helpers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae1-0/+8
In Revision 3 of the architecture, the RI and XI bits were added to the TLB to enable more secure access of memory pages. These bits (along with the Dirty bit) allow the implementation of read-only, write-only, no-execute access policies for mapped pages. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-24target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae1-6/+6
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1413982829-27225-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-14target-mips/op_helper.c: Remove unused do_lbu() functionPeter Maydell1-1/+0
The do_lbu() function defined by the expansion of HELPER_LD() is never used, so don't define it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim1-0/+111
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae1-0/+104
In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions. In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been updated yet. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-13target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim1-0/+23
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-08-07target-mips: Ignore unassigned accesses with KVMJames Hogan1-0/+11
MIPS registers an unassigned access handler which raises a guest bus error exception. However this causes QEMU to crash when KVM is enabled as it isn't called from the main execution loop so longjmp() gets called without a corresponding setjmp(). Until the KVM API can be updated to trigger a guest exception in response to an MMIO exit, prevent the bus error exception being raised from mips_cpu_unassigned_access() if KVM is enabled. The check is at run time since the do_unassigned_access callback is initialised before it is known whether KVM will be enabled. The problem can be triggered with Malta emulation by making the guest write to the reset region at physical address 0x1bf00000, since it is marked read-only which is treated as unassigned for writes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-18target-mips: implement UserLocal RegisterPetar Jovanovic1-1/+13
From MIPS documentation (Volume III): UserLocal Register (CP0 Register 4, Select 2) Compliance Level: Recommended. The UserLocal register is a read-write register that is not interpreted by the hardware and conditionally readable via the RDHWR instruction. This register only exists if the Config3-ULRI register field is set. Privileged software may write this register with arbitrary information and make it accessible to unprivileged software via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini1-5/+1
This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05softmmu: commonize helper definitionsPaolo Bonzini1-14/+0
They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini1-1/+0
Prepare for moving softmmu_header.h inclusion out of .c files Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-05softmmu: make do_unaligned_access a method of CPUPaolo Bonzini1-6/+5
We will reference it from more files in the next patch. To avoid ruining the small steps we're making towards multi-target, make it a method of CPU rather than just a global. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-1/+1
Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell1-1/+1
Add U suffix to various places where we shift a 1 left by 31, to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+3
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-2/+9
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-1/+1
This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-2/+2
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-3/+4
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber1-3/+6
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-1/+2
Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-10target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic1-3/+38
Description of UFR feature: Required in MIPS32r5 if floating point is implemented and user-mode FR switching is supported. The UFR register allows user-mode to clear StatusFR by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by executing a CFC1 to UFR. helper_ctc1 has been extended with an additional parameter rt to check requirements for UFR feature. Definition of mips32r5-generic has been modified to include support for UFR. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic1-0/+6
Add CP0_Config5, define rw_bitmask and enable modifications. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic1-0/+6
Add CP0_Config4, define rw_bitmask. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
2013-09-03cpu: Use QTAILQ for CPU listAndreas Färber1-6/+4
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand macros. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29target-mips: Remove assignment to a variable which is never usedStefan Weil1-1/+0
This assignment causes a compiler warning for compilations with the compiler option -Wunused-but-set-variable (which is included with -Wextra). Removing it allows using -Wextra for QEMU code without suppressing too many extra warnings. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-13/+12
Move next_cpu from CPU_COMMON to CPUState. Move first_cpu variable to qom/cpu.h. gdbstub needs to use CPUState::env_ptr for now. cpu_copy() no longer needs to save and restore cpu_next. Acked-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Rebased, simplified cpu_copy()] Signed-off-by: Andreas Färber <afaerber@suse.de>
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