riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2007-04-29	Kill broken host register definitions, thanks to Paul Brook and Herve	ths	1	-2/+0
2007-04-19	Update comment. We can't easily adhere to the architecture spec because	ths	1	-3/+3
2007-04-17	Choose number of TLBs at runtime, by Herve Poussineau.	ths	1	-1/+0
2007-04-11	Throw RI for invalid MFMC0-class instructions. Introduce optional	ths	1	-0/+5
2007-04-01	Actually enable 64bit configuration.	ths	1	-4/+1
2007-03-21	Move mips CPU specific initialization to translate_init.c.	ths	1	-37/+0
2007-03-18	MIPS -cpu selection support, by Herve Poussineau.	ths	1	-26/+0
2007-02-28	MIPS FPU dynamic activation, part 1, by Herve Poussineau.	ths	1	-9/+4
2006-12-21	Preliminiary MIPS64 support, disabled by default due to performance impact.	ths	1	-3/+10
2006-12-06	Add MIPS32R2 instructions, and generally straighten out the instruction	ths	1	-16/+34
2006-12-06	MIPS TLB performance improvements, by Daniel Jacobowitz.	ths	1	-0/+1
2006-06-14	mips config fixes (initial patch by Stefan Weil)	bellard	1	-11/+14
2006-06-14	MIPS FPU support (Marius Goeger)	bellard	1	-3/+9
2005-07-02	MIPS target (Jocelyn Mayer)	bellard	1	-0/+58