aboutsummaryrefslogtreecommitdiff
path: root/target-mips/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2016-01-23target-mips/cpu.h: Fix spell errorDongxue Zhang1-1/+1
2015-11-24target-mips: flush QEMU TLB when disabling 64-bit addressingLeon Alrae1-1/+17
2015-10-30target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim1-0/+1
2015-10-29target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6Leon Alrae1-1/+6
2015-10-29target-mips: move the test for enabled interrupts to a separate functionLeon Alrae1-14/+15
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson1-1/+0
2015-10-07target-mips: Add delayed branch state to insn_startRichard Henderson1-0/+1
2015-09-25mips: Remove ELF_MACHINE from cpu.hPeter Crosthwaite1-2/+0
2015-09-18target-mips: improve exception handlingPavel Dovgaluk1-0/+24
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-1/+1
2015-08-13target-mips: update mips32r5-generic into P5600Yongbok Kim1-1/+1
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite1-1/+1
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae1-0/+1
2015-06-12target-mips: add CP0.PageGrain.ELPA supportLeon Alrae1-2/+25
2015-06-12target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae1-7/+7
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae1-0/+1
2015-06-11target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae1-2/+11
2015-03-11Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell1-2/+17
2015-03-11target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae1-0/+17
2015-03-11target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae1-2/+0
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-1/+0
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki1-0/+12
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki1-3/+5
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki1-3/+4
2014-12-16target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki1-0/+89
2014-12-16target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki1-4/+4
2014-11-07mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki1-0/+13
2014-11-03target-mips: remove duplicated mips/ieee mapping functionYongbok Kim1-0/+4
2014-11-03target-mips: add MSA defines and data structureYongbok Kim1-2/+50
2014-11-03target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae1-1/+2
2014-11-03target-mips: implement forbidden slotLeon Alrae1-1/+2
2014-11-03target-mips: add Config5.SBRILeon Alrae1-2/+9
2014-11-03target-mips: update cpu_save/cpu_load to support new registersLeon Alrae1-1/+1
2014-11-03target-mips: add BadInstr and BadInstrP supportLeon Alrae1-0/+6
2014-11-03target-mips: add TLBINV supportLeon Alrae1-0/+7
2014-11-03target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae1-1/+4
2014-11-03target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae1-0/+4
2014-11-03target-mips: add RI and XI fields to TLB entryLeon Alrae1-0/+11
2014-11-03target-mips: add KScratch registersLeon Alrae1-0/+3
2014-10-14target-mips: fix broken MIPS16 and microMIPSYongbok Kim1-6/+7
2014-10-13target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae1-4/+14
2014-06-18target-mips: implement UserLocal RegisterPetar Jovanovic1-4/+7
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini1-0/+1
2014-03-27target-mips: Avoid shifting left into sign bitPeter Maydell1-1/+1
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber1-0/+1
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber1-3/+2
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-28/+0
2014-02-10target-mips: add support for CP0_Config5Petar Jovanovic1-0/+10
2014-02-10target-mips: add support for CP0_Config4Petar Jovanovic1-0/+3
generated by cgit v1.1 at 2024-12-24 00:50:42 +0000