aboutsummaryrefslogtreecommitdiff
path: root/target-mips/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2008-02-12Make MIPS MT implementation more cache friendly.ths1-4/+4
2007-12-30MIPS COP1X (and related) instructions, by Richard Sandiford.ths1-7/+11
2007-12-26De-cruft exception definitions, and implement nicer debug output.ths1-15/+12
2007-12-25Improved PABITS handling, and config register fixes.ths1-0/+2
2007-11-10added cpu_model parameter to cpu_init()bellard1-4/+2
2007-11-09Move kernel loader parameters from the cpu state to being board specific.ths1-5/+0
2007-10-28Implement missing MIPS supervisor mode bits.ths1-10/+16
2007-10-20Handle IBE on MIPS properly.ths1-0/+3
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-0/+11
2007-10-12Unify '-cpu ?' option.j_mayer1-0/+1
2007-09-27Move get_sp_from_cpustate from cpu.h to target_signal.h.ths1-5/+0
2007-09-27linux-user sigaltstack() syscall, by Thayne Harbaugh.ths1-0/+5
2007-09-25Optimise instructions accessing CP0, by Aurelien Jarno.ths1-9/+10
2007-09-24Per-CPU instruction decoding implementation, by Aurelien Jarno.ths1-0/+1
2007-09-06Partial support for 34K multithreading, not functional yet.ths1-41/+198
2007-06-23Handle MIPS64 SEGBITS value correctly.ths1-0/+2
2007-06-03Move target-specific defines to the target directories.ths1-0/+6
2007-05-31Don't kill the registered irqs on reset.ths1-3/+4
2007-05-30Fix CPU (re-)selection on reset.ths1-1/+4
2007-05-29Fix usermode check, thanks Aurelien Jarno.ths1-1/+1
2007-05-29Don't check the FPU state for each FPU instruction, use hflags toths1-3/+5
2007-05-28Handle PX/UX status flags correctly, by Aurelien Jarno.ths1-0/+1
2007-05-23The 24k wants more watch and srsmap registers.ths1-2/+2
2007-05-18- Move FPU exception handling into helper functions, since they are big.ths1-3/+3
2007-05-13MIPS linux-user update.ths1-0/+1
2007-05-13MIPS TLB style selection at runtime, by Herve Poussineau.ths1-8/+24
2007-05-07MIPS 64-bit FPU support, plus some collateral bugfixes in theths1-19/+25
2007-04-17Choose number of TLBs at runtime, by Herve Poussineau.ths1-0/+1
2007-04-07Unify IRQ handling.pbrook1-0/+2
2007-04-0564bit MIPS FPUs have 32 registers.ths1-2/+1
2007-03-30Fix typo, suggested by Ben Taylor.ths1-1/+1
2007-03-30Sanitize mips exception handling.ths1-2/+0
2007-03-23Fix enough FPU/R2 support to get 24Kf going.ths1-0/+2
2007-03-18MIPS -cpu selection support, by Herve Poussineau.ths1-0/+5
2007-03-02MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths1-0/+4
2007-02-28MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths1-3/+1
2007-02-20Replace TLSZ with TARGET_FMT_lx.ths1-7/+0
2007-01-24EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths1-1/+1
2007-01-24Reworking MIPS interrupt handling, by Aurelien Jarno.ths1-0/+1
2007-01-23Implementing dmfc/dmtc.ths1-33/+34
2007-01-22Fix PageMask handling, second part.ths1-2/+1
2006-12-23Check ELF binaries for machine type and endianness.ths1-0/+2
2006-12-21Scrap SIGN_EXTEND32.ths1-4/+1
2006-12-21Preliminiary MIPS64 support, disabled by default due to performance impact.ths1-7/+22
2006-12-06Add MIPS32R2 instructions, and generally straighten out the instructionths1-4/+55
2006-12-06Halt/reboot support for Linux, by Daniel Jacobowitz. This is a band-aidths1-1/+7
2006-12-06MIPS TLB performance improvements, by Daniel Jacobowitz.ths1-1/+2
2006-06-14Solaris/SPARC host port (Ben Taylor)bellard1-0/+7
2006-06-14use constants for TLB handling (Thiemo Seufer)bellard1-1/+1
2006-06-14mips config fixes (initial patch by Stefan Weil)bellard1-1/+1