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AgeCommit message (Expand)AuthorFilesLines
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson4-9/+4
2014-05-24lm32: remove lm32_sysMichael Walle1-10/+0
2014-05-24target-lm32: add semihosting supportMichael Walle5-2/+238
2014-05-14savevm: Remove all the unneeded version_minimum_id_old (rest)Juan Quintela1-4/+2
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-3/+3
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+1
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber1-1/+1
2014-03-13exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-2/+7
2014-03-13exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-2/+5
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-4/+1
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-3/+3
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-5/+8
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber4-5/+7
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2-4/+5
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2-8/+10
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber4-5/+9
2014-03-13cpu: Factor out cpu_generic_init()Andreas Färber1-12/+1
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-5/+6
2014-02-04target-lm32: stop VM on illegal or unknown instructionMichael Walle3-38/+86
2014-02-04target-lm32: add breakpoint/watchpoint supportMichael Walle7-8/+179
2014-02-04target-lm32: move model features to LM32CPUMichael Walle5-142/+215
2014-02-04target-lm32: kill cpu_abort() callsMichael Walle1-32/+40
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+2
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
2013-07-29lm32_juart: Relocate and tidy headerAndreas Färber1-1/+1
2013-07-29cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber1-2/+4
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber4-4/+16
2013-07-27gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber1-8/+8
2013-07-27target-lm32: Move cpu_gdb_{read,write}_register()Andreas Färber1-0/+85
2013-07-26cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber1-0/+1
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber3-3/+9
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-3/+4
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber1-5/+0
2013-07-23cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber1-0/+8
2013-07-09cpu: Move reset logging to CPUStateAndreas Färber1-5/+0
2013-07-09log: Change log_cpu_state[_mask]() argument to CPUStateAndreas Färber2-3/+3
2013-07-09target-lm32: Change gen_intermediate_code_internal() argument to LM32CPUAndreas Färber1-4/+5
2013-07-09target-lm32: gen_intermediate_code_internal() should be inlinedAndreas Färber1-2/+3
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber1-1/+1
2013-07-09linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell1-14/+0
2013-06-28cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber1-2/+0
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber3-2/+7
2013-04-08hw: move headers to include/Paolo Bonzini2-3/+3
2013-03-18target-lm32: use HELPER() macroMichael Walle1-10/+10
2013-03-18target-lm32: flush tlb after clearing envMichael Walle1-2/+2
2013-03-18target-lm32: remove dead codeMichael Walle1-10/+0
2013-03-18target-lm32: fix cmpgui and cmpgeui opcodesMichael Walle1-4/+14
2013-03-18target-lm32: don't log cpu state in translationMichael Walle1-5/+0
2013-03-18target-lm32: fix debug memory accessMichael Walle1-1/+6
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