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AgeCommit message (Expand)AuthorFilesLines
2008-05-21converted env access to TCGbellard2-67/+32
2008-05-21convert eflags manipulation insns to TCGbellard5-148/+46
2008-05-21convert remaining segment handling to TCGbellard3-49/+38
2008-05-21converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LARbellard4-61/+39
2008-05-21suppressed no longer used opsbellard2-17/+0
2008-05-21converted INTO/CMPXCHG8B to TCGbellard4-20/+12
2008-05-21converted BCD ops to TCGbellard2-38/+6
2008-05-21converted MUL/IMUL to TCGbellard3-133/+129
2008-05-18converted string OPs and LOOP insns to TCGbellard3-294/+147
2008-05-18fixed INC/DEC condition codesbellard1-1/+1
2008-05-17converted sign extension ops to TCGbellard2-76/+31
2008-05-17MONITOR insn address generation fix - converted XLAT to TCGbellard2-40/+20
2008-05-17BSR/BSF TCG conversionbellard4-72/+54
2008-05-17converted bit test operations to TCGbellard2-98/+53
2008-05-17moved eflags computation outside op.cbellard4-293/+296
2008-05-17converted adc, sbb, cmpxchg to TCGbellard3-305/+151
2008-05-17converted condition code supprot to TCG - converted shift ops to TCGbellard9-1132/+762
2008-05-15converted more helpers to TCG - fixed some SVM issuesbellard10-485/+404
2008-05-13i386 specific TODObellard1-0/+29
2008-05-12compilation fixbellard1-1/+3
2008-05-12converted more helpers to TCGbellard5-647/+498
2008-05-12removed unused codebellard1-6/+0
2008-05-12FPU fixesbellard1-11/+11
2008-05-12converted x87 FPU ops to TCGbellard5-945/+756
2008-05-12converted SSE/MMX ops to TCGbellard6-671/+715
2008-05-12use TCG for MMX/SSE memory accessesbellard3-221/+58
2008-05-12char is only for stringsbellard1-3/+3
2008-05-10no need to define global registers in cpu-exec.cbellard1-41/+4
2008-05-04Correctly save and restore env->a20_mask now that it is a 64-bitaurel321-2/+6
2008-05-04remove target ifdefs from vl.caurel321-0/+264
2008-04-28Factorize code in translate.caurel321-0/+23
2008-04-27Use correct types to enable > 2G support, based on a patch fromaurel322-3/+26
2008-04-22Fix PHYS_ADDR_MASK: upper bits of a PTE are reserved so they are 52 bitsaurel321-1/+2
2008-04-22x86/x86-64 MMU PAE fixesaurel322-20/+24
2008-04-13x86: Introduce CPU_INTERRUPT_NMIaurel323-2/+7
2008-04-11Remove osdep.c/qemu-img code duplicationaurel321-0/+1
2008-04-11Remove unused phys_ram_base definition from target-i386/helper.c.aurel321-1/+0
2008-04-09Check for 3DNow! CPUID at translation timeaurel321-2/+13
2008-04-08Fix typo in x86 CPU definitions introduced in r4181aurel321-1/+1
2008-04-08Remove hardcoded values in x86 CPU definitionsaurel321-4/+11
2008-04-083DNow! instruction set emulationaurel324-10/+246
2008-03-28x86-64: recompute DF after eflags has been modified when emulating SYSCALLaurel321-0/+1
2008-03-09 Fix some functions declared () rather than (void) (Ian Jackson)blueswir12-2/+2
2008-02-24 More helper types, rearrange generic definitionsblueswir11-64/+0
2008-02-03Add TCG variable opaque type.pbrook1-3/+3
2008-02-03NMI and INTR events injection should not be handled as software interrupts (B...balrog1-2/+2
2008-02-03Make SVM env->cr[8] a valid register (patch from TeLeMan).balrog2-2/+6
2008-02-01use the TCG code generatorbellard6-1160/+794
2007-12-24Correct the max cpuid level for each x86 cpu model (Dan Kenigsberg).balrog1-1/+8
2007-12-24SVM enabled processor should provide cpuid Fn8000_000A (Bernhard Kauer).balrog2-1/+7
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