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2014-01-07target-i386: Remove gen_op_movl_T0_T1Richard Henderson1-6/+1
Replace it with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_andl_T0_imRichard Henderson1-11/+9
Replace it with its definition. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_andl_T0_ffffRichard Henderson1-25/+18
Replace it with tcg_gen_ext16u_tl. In four places we can combine that with a previous move into cpu_T[0], and in one place we can infer that the zero-extension has already happened via the previous load. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_movtl_T*_imRichard Henderson1-13/+3
Propagate the definitions into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_mov*_A0_imRichard Henderson1-15/+2
Propagate the definitions into all users. In two cases, this allows us to share code between the 32-bit and 64-bit immediate moves. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_movl_T0_im*Richard Henderson1-20/+10
Propagate the definitions into all users. The only time that gen_op_movl_T1_imu was used, the input was type 'unsigned', so the replacement works identically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_movl_T0_im*Richard Henderson1-22/+10
Propagate the definition of gen_op_movl_T0_im to all users. The function gen_op_movl_T0_imu was unused. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_movl_T0_0Richard Henderson1-11/+6
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Tidy extend + moveRichard Henderson1-9/+5
For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp into a 64-bit temp before storing into the hardware register. We do need the extension for the MO_8/MO_16 cases, in order for the deposit_tl operation to work, so leave those alone. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Tidy extend + storeRichard Henderson1-17/+17
We can now use tcg_gen_qemu_st_i32 directly to avoid the extension. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Tidy load + truncateRichard Henderson1-20/+19
We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32Richard Henderson1-6/+3
For the 16 and 32-bit cases, we don't need to truncate via a temporary register. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Use MO_BE for movbeRichard Henderson1-35/+5
Fold the bswap into the memory operation. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove unused arguments to gen_lea_modrmRichard Henderson1-77/+69
The reg_ptr and offset_ptr outputs are universally unused. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Tidy movslRichard Henderson1-5/+1
Always perform a sign-extending load. In the extremely unlikely case that we've used an 0x66 prefix, the extension to 64-bits is unnecessary but not wrong; the store will still examine only 16 bits. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Tidy mov[sz][bw]Richard Henderson1-11/+12
We can use the MO_SIGN bit to tidy the reg-reg switch statement as well as pass it on to gen_op_ld_v, eliminating one call. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Fix typo in gen_push_T1Richard Henderson1-1/+1
By inspection, obviously we should be storing T[1] not T[0]. This could only happen for x86_64 in 64-bit mode with 0x66 prefix to call insn -- i.e. never. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_st_T1_A0Richard Henderson1-7/+2
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_st_T0_A0Richard Henderson1-43/+40
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Introduce gen_op_st_rm_T0_A0Richard Henderson1-61/+24
Too many places have the same test vs OR_TMP0 to indicate a write back to memory. Hoist that to a subroutine. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_lds_T0_A0Richard Henderson1-9/+4
Replace its users by gen_op_ld_v with the MO_SIGN bit set. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_ld_T1_A0Richard Henderson1-14/+9
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_ldu_T0_A0Richard Henderson1-10/+5
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Remove gen_op_ld_T0_A0Richard Henderson1-41/+36
Propagate its definition into all users. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Replace OT_* constants with MO_* constantsRichard Henderson1-360/+354
The MO_8/16/32/64 constants have the same encoding and meaning as the OT_BYTE/WORD/LONG/QUAD. Since we rely on them being the same, for the qemu_ld/st helpers, standardize on the common names. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Use new tcg_gen_qemu_st_* helpersRichard Henderson1-41/+34
In preference to the older helpers. Stores only in this patch. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Use new tcg_gen_qemu_ld_* helpersRichard Henderson1-53/+31
In preference to the older helpers. Loads only in this patch. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Stop encoding DisasContext.mem_indexRichard Henderson1-42/+25
Now that we don't combine mem_index with operand size info, we don't need to encode it. Which tidies many places that access it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-07target-i386: Push DisasContext into load/store helpersRichard Henderson1-161/+170
Rather than add s->mem_index into a combined size+mem_index argument, pass the context down. This will allow cleaning up s->mem_index later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-21target-i386: Fix addr32 prefix in gen_lea_modrmRichard Henderson1-45/+47
Fix the following run-test-x86_64 testsuite failures: -lea (%%eax) = 0000000000000001 -lea (%%ebx) = 0000000000000002 -lea (%%ecx) = 0000000000000004 -lea (%%edx) = 0000000000000008 -lea (%%esi) = 0000000000000010 -lea (%%edi) = 0000000000000020 +lea (%%eax) = 0000abcc00000001 +lea (%%ebx) = 0000abcf00000002 +lea (%%ecx) = 0000abc900000004 +lea (%%edx) = 0000abc500000008 +lea (%%esi) = 0000abdd00000010 +lea (%%edi) = 0000abed00000020 In addition, reduce ifdeffery and minimize the number of TCG ops produced during address computation. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1384219016-5170-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-21target-i386: yield to another VCPU on PAUSEPaolo Bonzini1-1/+4
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown. The problem shows up as soon as FreeBSD turns out its periodic (~1 ms) tick, but the timers are only the trigger for a pre-existing problem. Before the offending patch, setting a timer did a timer_settime system call. After, setting the timer exits the event loop (which uses poll) and reenters it with a new deadline. This does not cause any slowdown; the difference is between one system call (timer_settime and a signal delivery (SIGALRM) before the patch, and two system calls afterwards (write to a pipe or eventfd + calling poll again when re-entering the event loop). Unfortunately, the exit/enter causes the main loop to grab the iothread lock, which in turns kicks the VCPU thread out of execution. This causes TCG to execute the next VCPU in its round-robin scheduling of VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause" instruction in its idle loop which only burns cycles without any progress. As soon as the timer tick expires, the first VCPU runs the interrupt handler but very soon it sets it again---and QEMU then goes back doing nothing in the second VCPU. The fix is to make the pause instruction do "cpu_loop_exit". Cc: Richard Henderson <rth@twiddle.net> Reported-by: Luigi Rizzo <rizzo@iet.unipi.it> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson1-4/+0
No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-12target-i386: Only provide CMOV and friends if feature bit setPeter Maydell1-0/+19
The instructions CMOVcc, FCMOVcc and F[U]COMI[P] should only be present if the CMOV feature bit is set. Add missing feature bit checks so we correctly fault if emulating a 486 or 586. This fixes bug LP:1201446. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson1-1/+1
And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber1-2/+3
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09target-i386: Change gen_intermediate_code_internal() argument to X86CPUAndreas Färber1-4/+5
Also use bool type while at it. Prepares for moving singlestep_enabled field to CPUState. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-31target-i386: Fix aflag logic for CODE64 and the 0x67 prefixRichard Henderson1-15/+15
The code reorganization in commit 4a6fd938 broke handling of PREFIX_ADR. While fixing this, tidy and comment the code so that it's more obvious what's going on in setting both aflag and dflag. The TARGET_X86_64 ifdef can be eliminated because CODE64 expands to the constant zero when TARGET_X86_64 is undefined. Cc: Paolo Bonzini <pbonzini@redhat.com> Reported-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1369855851-21400-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-05-10target-i386: ROR r8/r16 imm instruction fixAurelien Jarno1-0/+1
Fix EFLAGS corruption by ROR r8/r16 imm instruction located at the end of the TB, similarly to commit 089305ac for the non-immediate case. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-02target-i386: Replace cpuid_*features fields with a feature word arrayEduardo Habkost1-5/+5
This replaces the feature-bit fields on both X86CPU and x86_def_t structs with an array. With this, we will be able to simplify code that simply does the same operation on all feature words (e.g. kvm_check_features_against_host(), filter_features_for_kvm(), add_flagname_to_bitmaps(), CPU feature-bit property lookup/registration, and the proposed "feature-words" property) The following field replacements were made on X86CPU and x86_def_t: (cpuid_)features -> features[FEAT_1_EDX] (cpuid_)ext_features -> features[FEAT_1_ECX] (cpuid_)ext2_features -> features[FEAT_8000_0001_EDX] (cpuid_)ext3_features -> features[FEAT_8000_0001_ECX] (cpuid_)ext4_features -> features[FEAT_C000_0001_EDX] (cpuid_)kvm_features -> features[FEAT_KVM] (cpuid_)svm_features -> features[FEAT_SVM] (cpuid_)7_0_ebx_features -> features[FEAT_7_0_EBX] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-04-20i386 ROR r8/r16 instruction fixPavel Dovgaluk1-0/+1
Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the TB. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-13target-i386: add AES-NI instructionsAurelien Jarno1-0/+7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-13target-i386: add pclmulqdq instructionAurelien Jarno1-0/+3
Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-01target-i386: SSE4.1: fix pinsrb instructionAurelien Jarno1-2/+2
gen_op_mov_TN_reg() loads the value in cpu_T[0], so this temporary should be used instead of cpu_tmp0. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-23target-i386: Fix flags computation for ADOXRichard Henderson1-1/+1
When starting from CC_OP_DYNAMIC, and issuing adox before adcx, a typo used the wrong value for the resulting CC_OP. Cc: Blue Swirl <blauwirbel@gmail.com> Reported-by: Torbjorn Granlund <tg@gmplib.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-22Fix typos and misspellingsPeter Maydell1-1/+1
Fix various typos and misspellings. The bulk of these were found with codespell. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-27target-i386: Use mulu2 and muls2Richard Henderson1-111/+56
These correspond very closely to the insns that we're emulating. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-i386: Use add2 to implement the ADX extensionRichard Henderson1-11/+9
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-19target-i386: Use movcond to implement shiftd.Richard Henderson1-141/+106
With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-19target-i386: Discard CC_OP computation in set_cc_op alsoRichard Henderson1-3/+11
The shift and rotate insns use movcond to set CC_OP, and thus achieve a conditional EFLAGS setting. By discarding CC_OP in a later flags setting insn, we can discard that movcond. Signed-off-by: Richard Henderson <rth@twiddle.net>
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