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2008-03-14* Add a model of the ETRAX interrupt controller.edgar_igl1-56/+51
* Clean up the interrupt handling a bit. * Connect some NOR flash to the test board. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4055 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-01* target-cris/op.c: Make sure the bit-test insn only updates the XNZ flags.edgar_igl2-11/+14
* target-cris/helper.c: Update ERP for user-mode simulation aswell. * hw/etraxfs_timer.c: Support multiple timers. * hw/etraxfs_ser.c: Multiple ports, the data just goes to stdout. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4004 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-28Cut the translation block after translating a break insn. This avoids an ↵edgar_igl1-1/+6
issue where QEMU finds an illegal CRIS insn while the guest is returning through a signal return trampoline. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3997 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-28More consistent naming for CRIS register-number macros.edgar_igl5-74/+73
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3996 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-25Silently ignore CRIS cache flushes, instead of aborting due to unknown insn.edgar_igl2-2/+17
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3990 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-01use the TCG code generatorbellard2-53/+10
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-01-14Optimize clear insns by treating support reg P0 specially andbalrog2-19/+30
add missing micro-op RETURN's (Edgar E. Iglesias). git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3913 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11fixed invalid typebellard1-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-10added cpu_model parameter to cpu_init()bellard2-6/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29Adjust s390 addresses (the MSB is defined as "to be ignored").ths1-1/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-28Use the shiny new clz helpers.ths2-6/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3464 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer6-10/+23
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08CRIS MMU emulation, by Edgar E. Iglesias.ths2-0/+167
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3362 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08The remainder of CRIS CPU emulation files, by Edgar E. Iglesias.ths6-0/+680
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3361 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08CRIS micro-ops, by Edgar E. Iglesias.ths1-0/+1289
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3360 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08CRIS insn decoding macros, by Edgar E. Iglesias.ths1-0/+126
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3359 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08CRIS instruction translation, by Edgar E. Iglesias.ths1-0/+2507
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3358 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08CRIS disassembler, originally from binutils, by Edgar E. Iglesias.ths1-0/+366
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3356 c046a42c-6fe2-441c-8c8c-71466251a162