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path: root/target-cris/mmu.h
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2012-03-14target-cris: Don't overuse CPUStateAndreas Färber1-3/+3
Scripted conversion: sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc] sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2010-07-05cris: Avoid debug clobbering for both I & D MMU state.Edgar E. Iglesias1-1/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@axis.com>
2009-04-25CRIS: cris_mmu_result_t -> cris_mmu_resultEdgar E. Iglesias1-2/+2
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2009-01-26CRIS: Init the feedback shiftreg used for randomizing TLB sets.edgar_igl1-0/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6463 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04CRIS: Remove unused pfn member from mmu translation results.edgar_igl1-1/+0
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6160 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-13CRIS: Improve TLB management and handle delayslots at page boundaries.edgar_igl1-1/+1
* Dont flush the entire qemu tlb when the $pid changes. Instead we go through the guests TLB and choose entries that need to be flushed. * Add env->dslot and handle delayslots at pageboundaries. * Remove some unused code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4450 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-07CRIS: More TCG conversion.edgar_igl1-1/+1
* Convert moves to/from support function regs (including TLB updates) to TCG. * SCC no longer requires T0 to strictly be 0 or 1, relaxed to 0 or non-zero. * Convert the the condition code evaluation to TCG. * Convert rfe into a helper and TCG. * Convert evaluate_bcc and setf to TCG. * Convert clrf to TCG. * Convert CRIS exception raising to TCG. * Convert btst to TCG. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4376 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-02CRIS updates:edgar_igl1-0/+1
* Support both the I and D MMUs and improve the accuracy of the MMU model. * Handle the automatic user/kernel stack pointer switching when leaving or entering user mode. * Move the CCS evaluation into helper funcs. * Make sure user-mode cannot change flags only writeable in kernel mode. * More conversion of the translator into TCG. * Handle exceptions while in a delayslot. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4299 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-14Model more parts of the ETRAX mmu (still alot missing).edgar_igl1-6/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4056 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer1-1/+1
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-08CRIS MMU emulation, by Edgar E. Iglesias.ths1-0/+20
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3362 c046a42c-6fe2-441c-8c8c-71466251a162
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