riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2009-01-04	Update FSF address in GPL/LGPL boilerplate	aurel32	1	-1/+1
2008-10-08	CRIS: Partial EXS reg support and fixes for SPC.	edgar_igl	1	-0/+3
2008-10-07	CRIS: Fix brk 8 and add S-flag emulation.	edgar_igl	1	-1/+1
2008-09-05	CRIS: Mask off the cache selection bit after MMU translations.	edgar_igl	1	-1/+5
2008-09-03	CRIS: Remove redundant code.	edgar_igl	1	-2/+0
2008-06-09	CRIS: Emulate NMIs.	edgar_igl	1	-8/+11
2008-05-27	CRIS: Restructure the translator to allow for better code generation.	edgar_igl	1	-2/+1
2008-05-13	CRIS: Improve TLB management and handle delayslots at page boundaries.	edgar_igl	1	-6/+13
2008-05-06	CRIS MMU Updates	edgar_igl	1	-2/+9
2008-05-02	CRIS updates:	edgar_igl	1	-35/+43
2008-03-14	* Add a model of the ETRAX interrupt controller.	edgar_igl	1	-56/+51
2008-03-01	* target-cris/op.c: Make sure the bit-test insn only updates the XNZ flags.	edgar_igl	1	-10/+8
2008-02-28	More consistent naming for CRIS register-number macros.	edgar_igl	1	-12/+9
2007-10-28	Use the shiny new clz helpers.	ths	1	-2/+2
2007-10-14	Replace is_user variable with mmu_idx in softmmu core,	j_mayer	1	-4/+4
2007-10-08	The remainder of CRIS CPU emulation files, by Edgar E. Iglesias.	ths	1	-0/+173